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Alpha 21264/EV67 Hardware Reference Manual
Cache and External Interfaces 4–35
System Port
1. The SysDataInValid_L signal must be asserted for both cycles of a SysDc fill
command, and two quadwords of data must be delivered to the 21264/EV67 in suc-
ceeding bit-clock cycles with the appropriate timing in reference to the SysDc fill
command (SYSDC_DELAY + 10 CPU cycles).
2. Any number of bubble cycles can be introduced within the fill by deasserting
SysDataInValid_L between octaword transfers.
3. The transfer of fill data can continue by asserting SysDataInValid_L for at least
two bit-clock cycles, and delivering data SYSDC_DELAY + 10 CPU cycles after
the assertion of
SysDataInValid_L.
4. The 21264/EV67 must see SysDataInValid_L asserted for eight data cycles in
order to complete a fill. When the eighth cycle of an asserted SysDataInValid_L is
perceived by the 21264/EV67, the transfer is complete.
5. Systems that do not use SysDataInValid_L may tie the pin to the asserted state.
If SYSDC_DELAY is greater than the bit-time of a transfer, the SysDataInValid_L
signal must be internally pipelined. To enable the correct sampling of
SysDataInValid_L, the 21264/EV67 provides a delay, with Cbox CSR
DATA_VALID_DELAY[1:0], that is equal to SYSDC_DELAY[4:0]/bit-time. For
example, consider system 1 in Table 4–26, which has a SYSDC_DELAY of five
GCLKs. Running at a bit-time of 1.5X, the DATA_VALID_DELAY[1,0] is pro-
grammed with a value of three.
SysDataOutValid_L
Systems that use a ratio of 1:1 for SYSCLK:INT_FWD_CLK may control the flow of
data out of the 21264/EV67 by using SysDataOutValid_L as follows:
1. The SysDataOutValid_L pin must be asserted for at least the first cycle of the
SysDc write command that initiates a write transfer.
2. Any number of bubble cycles may be introduced between quadword transfers by
deasserting SysDataOutValid_L.
3. The 21264/EV67 must see the SysDataOutValid_L signal asserted for eight data
cycles to complete a write transaction, and when the eighth cycle of an asserted
SysDataOutValid_L is perceived by the 21264/EV67, the transfer is complete.
4.7.8.5 SysFillValid_L
The SysFillValid_L pin, when asserted, validates the current memory and I/O data
transfer into the 21264/EV67. The system designer may tie this pin to the asserted state
(validating all fills), or use it to enable or cancel fills as they progress. The 21264/EV67
samples SysFillValid_L at D1 time (when the 21264/EV67 samples the second data
cycle).
If SysFillValid_L is asserted at D1 time, the fill will continue uninterrupted. If it is not
asserted, the 21264/EV67 cancels the fill, but expects all eight QWs of data to arrive at
its system bus before continuing to the next fill. Also, the 21264/EV67 maintains the
state of the MAF, expecting another valid fill to the same MAF entry. Figure 4–6 illus-
trates SysFillValid_L timing.