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Alpha 21264/EV67 Hardware Reference Manual
Internal Processor Registers 5–41
Cbox CSRs and IPRs
5.4.5 Cbox Read Register (IPR) Description
The Cbox read register is read 6 bits at a time. Table 5–26 shows the ordering from LSB
to MSB.
Table 5–26 Cbox Read IPR Fields Description
Name Description
C_SYNDROME_1[7:0] If CMD is ChxToDirty, then C_SYNDROME_1 is X; otherwise, is syndrome for
upper QW in OW of victim that was scrubbed.
C_SYNDROME_0[7:0] If CMD is ChxToDirty, then C_SYNDROME_0 is X; otherwise, is syndrome for
lower QW in OW of victim that was scrubbed.
C_STAT[4:0]
1 Error status as specified only when Cbox WRITE_ONCE chain bit
SKEWED_ FILL_MODE[0] is clear; otherwise, error status is
generic DOUBLE_BIT_ERROR (1XXXX).
C_STS[3:0] If C_STAT equals xxx_MEM_ERR or xxx_BC_ERR, then C_STS contains the
status of the block as follows; otherwise, the value of C_STS is X:
C_ADDR[6:42] Address of last reported ECC or parity error. If C_STAT value is
DSTREAM_DC_ERR, only bits 6:19 are valid. If C_STAT value is
DOUBLE_BIT_ERROR and SKEWED_FILL_MODE[0] is set, then C_ADDR
is X.
Bits Error Status
0 0 0 0 0 Either no error, or error on a speculative load, or a Bcache vic-
tim read due to a Dcache/Bcache miss
0 0 0 0 1 BC_PERR (Bcache tag parity error)
0 0 0 1 0 DC_PERR (duplicate tag parity error)
0 0 0 1 1 DSTREAM_MEM_ERR
0 0 1 0 0 DSTREAM_BC_ERR
0 0 1 0 1 DSTREAM_DC_ERR
0 0 1 1 X PROBE_BC_ERR
0 1 0 0 0 Reserved
0 1 0 0 1 Reserved
0 1 0 1 0 Reserved
0 1 0 1 1 ISTREAM_MEM_ERR
0 1 1 0 0 ISTREAM_BC_ERR
0 1 1 0 1 Reserved
0 1 1 1 X Reserved
1 0 0 1 1 DSTREAM_MEM_DBL
1
1 0 1 0 0 DSTREAM_BC_DBL
1
1 1 0 1 1 ISTREAM_MEM_DBL
1
1 1 1 0 0 ISTREAM_BC_DBL
1
Bit Value Status of Block
7:4 Reserved
3 Parity
2 Valid
1 Dirty
0Shared