Filter
Top Products
Alpha 21264/EV67 Hardware Reference Manual
Initialization and Configuration 7–17
Reset State Machine
Figure 7–5 21264/EV67 Reset State Machine State Diagram
Table 7–11 21264/EV67 Reset State Machine State Descriptions
State Name Description
COLD Chip cold. Transitioned to WAIT_SETTLE with assertion of Reset_L, PLL_VDD, and
VDD.
WAIT_SETTLE PLL_VDD asserted; PLL at minimum frequency.
WAIT_NOMINAL Triggered by assertion of DCOK_H. PLL achieves a lock at X
div
and Z
div
divisors equal
16 and 32, respectively.
RAMP1 Triggered by Reset_L deassertion; X
div
and Z
div
divisors are changed to 2 and 4, respec-
tively, increasing the internal GCLK frequency. An internal duration counter is initial-
ized to count 4108 GCLK cycles.
WAIT_
SETTLE
[16,32]
WAIT_
NOMINAL
[16,32]
RAMP1
[2,4]
RAMP2
[1,2]
WAIT_ClkFwd
Rst0
WAIT_ClkFwd
Rst1
RUN
FAULT_
RESET
DOWN3
[16,32]
DOWN2
[2,4]
DOWN1
[1,2]
COLD
WAIT_
BiSI
WAIT_
BiST
BiSI
finished
Counter
finished
Reset_L
deasserted
Reset_L
asserted
DCOK_H
asserted
Counter
finished
ClkFwdRst_H
deasserted
Counter
finished
*No BiST/BiSI
on recovery from Fault
Reset
BiST
finished
ClkFwdRst_H
deasserted
Counter
finished
Reset_L
deasserted
Enabled
Interrupt
ClkFwdRst_H
asserted
Sleep Mode
or Reset_L
asserted
Out of
Sleep
Mode
Out of
FAULT_
RESET*
Counter
finished
Counter
finished &
Sleep Mode
Counter
finished &
not Sleep Mode
LKG-10982A-98WF
Reset_L
asserted
PLL Ramp Up
PLL Ramp Down
WAIT_
INTERRUPT
WAIT_
RESET
Numbers in "[,]" are
Xdiv and Zdiv divisors,
respectively