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Alpha 21264/EV67 Hardware Reference Manual
21264/EV67 Boundary-Scan Register B–1
B
21264/EV67 Boundary-Scan Register
This appendix contains the BSDL description of the 21264/EV67 boundary-scan regis-
ter.
B.1 Boundary-Scan Register
The Boundary-Scan Register (BSR) on the 21264/EV67 is 367 bits long. It is accessed
by the three public (SAMPLE, EXTEST, CLAMP) instructions. The register operation
for the public instructions is compliant with the IEEE 1149.1 standard.
The boundary-scan register covers all input, output, and bidirectional pins with the
exception of the compliance enable pins and pins that are power-supply-type or analog
in nature. The BSDL for the boundary-scan register is given in Section B.1.1.
B.1.1 BSDL Description of the Alpha 21264/EV67 Boundary-Scan Register
-------------------------------------------------------------------------------
-- alpha21264/EV67.bsdl
--The BSDL Description for EV6’s IEEE 1149.1 Circuits
-------------------------------------------------------------------------------
-- Revision History
--Rev Date Description
-- 1.0 Feb 99 First external release
-------------------------------------------------------------------------------
entity Alpha_21264/EV67 is-- (ref B.8)
generic (PHYSICAL_PIN_MAP :string := "PGA_EV6");-- (ref B.8.2)
port (-- (ref B.8.3)
TestStat_H :out bit ;
SromOE_L :out bit ;
SromClk_H :out bit ;
SromData_H :in bit ;
Reset_L :in bit ;
IRQ_H :in bit_vector (0 to 5) ;
DcOk_H :linkage bit ; -- Compliance enable input
NoConnect_0 :linkage bit ; -- n/c
NoConnect_1 :linkage bit ; -- n/c
PllBypass_H :linkage bit ;
FrameClk_H :linkage bit ;
FrameClk_L :linkage bit ;
ClkFwdRst_H :in bit ;
BcCheck_H :inout bit_vector (0 to 15);
BcData_H :inout bit_vector (0 to 127);
SysData_L :inout bit_vector (0 to 63) ;
SysCheck_L :inout bit_vector (0 to 7) ;
BcDataInClk_H :in bit_vector (0 to 7) ;
SysDataOutClk_L :out bit_vector (0 to 7) ;
Spare_7 :linkage bit_vector (0 to 7) ;