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2–24 Internal Architecture
Alpha 21264/EV67 Hardware Reference Manual
Special Cases of Alpha Instruction Execution
2.6.3 Prefetch, Evict Next: LDQ and HW_LDQ Instructions
The 21264/EV67 processes this instruction like a normal prefetch transaction (Read-
BlkSpec command), with one exception—if the load misses the Dcache, the addressed
cache block is allocated into the Dcache, but the Dcache set allocation pointer is left
pointing to this block. The next miss to the same Dcache line will evict the block. For
example, this instruction might be used when software is reading an array that is known
to fit in the offchip Bcache, but will not fit into the onchip Dcache. In this case, the
instruction ensures that the hardware provides the desired prefetch function without dis-
placing useful cache blocks stored in the other set within the Dcache.
The HW_LDQ instruction construct equates to the HW_LD instruction with the LEN
field set. See Table 6–3.
2.6.4 Prefetch with the LDx_L / STx_C Instruction Sequence
A prefetch within a dynamic 80-instruction window of a LDx_L instruction can cause
the subsequent STx_C to incorrectly succeed when all three references are to the same
64-byte cache block. Within that 80-instruction window, the proximity of the prefetch
to the LDx_L instruction directly affects the possibility of the incorrect behavior. Fur-
ther, if the prefetch issues before the LDx_L, the error cannot occur, and if the prefetch
issues after the LDx_L, the error can only occur when another processor is simulta-
neously acquiring the same lock.
2.7 Special Cases of Alpha Instruction Execution
This section describes the mechanisms that the 21264/EV67 uses to process irregular
instructions in the Alpha instruction set, and cases in which the 21264/EV67 processes
instructions in a non-intuitive way.
2.7.1 Load Hit Speculation
The latency of integer load instructions that hit in the Dcache is three cycles. Figure 2–
9 shows the pipeline timing for these integer load instructions. In Figure 2–9:
Symbol Meaning
Q Issue queue
R Register file read
E Execute
D Dcache access
B Data bus active