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5–30 Internal Processor Registers
Alpha 21264/EV67 Hardware Reference Manual
Mbox IPRs
Table 5–19 describes the Mbox control register fields.
Note: Superpage accesses are only allowed in kernel mode. Non-kernel mode ref-
erences to superpages result in access violations.
5.3.10 Dcache Control Register – DC_CTL
The Dcache control register (DC_CTL) is a write-only register that controls Dcache
activity. The contents of DC_CTL are initialized by chip reset as indicated. Figure 5–33
shows the Dcache control register.
Table 5–19 Mbox Control Register Fields Description
Name Extent Type Description
Reserved [63:6] ——
SMC[1:0] [5:4] WO,0 Speculative miss control (see Section 4.6.4).
SPE[2:0] [3:1] WO,0 Superpage mode enables.
SPE[2], when set, enables superpage mapping when VA[47:46] = 2. In this
mode, VA[43:13] are mapped directly to PA[43:13] and VA[45:44] are
ignored.
SPE[1], when set, enables superpage mapping when VA[47:41] = 7E
16
. In
this mode, VA[40:13] are mapped directly to PA[40:13] and PA[43:41] are
copies of PA[40] (sign extension).
SPE[0], when set, enables superpage mapping when VA[47:30] = 3FFFE
16
.
In this mode, VA[29:13] are mapped directly to PA[29:13] and PA[43:30] are
cleared.
Reserved [0] — —
Bits Meaning When Set
00 Allow full-time speculation.
01 Force full-time conservative mode. Make retries wait until retire,
force all new stores that do not hit dirty to retry, and cause prefetches
with modify intent (see Section 2.6.2) to behave like normal
prefetches.
10 Place 21264/EV67 in periodic conservative mode by using an 8-bit
counter to add by 4 each time a branch mispredict happens and sub-
tract by one each time a conditional branch retires. Enter conserva-
tive mode if the MSB of the counter is set.
11 Place 21264/EV67 in periodic conservative mode by using an 8-bit
countner to add by 8 each time a branch mispredict happens and sub-
tract by one each time a conditional branch retires. Enter conserva-
tive mode if the MSB of the counter is set.