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5–6 Internal Processor Registers
Alpha 21264/EV67 Hardware Reference Manual
Ibox IPRs
Figure 5–6 Virtual Address Format Register (VA_48 = 1, VA_FORM_32 = 0)
Figure 5–7 shows VA_FORM when VA_CTL(VA_48) equals 0 and
VA_CTL(VA_FORM_32) equals 1.
Figure 5–7 Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 1)
5.2 Ibox IPRs
This section describes the internal processor registers that control Ibox functions.
5.2.1 ITB Tag Array Write Register – ITB_TAG
The ITB tag array write register (ITB_TAG) is a write-only register. The ITB tag array
is written by way of this register. A write transaction to ITB_TAG writes a register out-
side the ITB array. When a write to the ITB_PTE register is retired, the contents of both
the ITB_TAG and ITB_PTE registers are written into the ITB entry. The specific ITB
entry that is written is determined by a round-robin algorithm; the algorithm writes to
entry number 0 as the first entry after the 21264/EV67 is reset. Figure 5–8 shows the
ITB tag array write register.
Figure 5–8 ITB Tag Array Write Register
5.2.2 ITB PTE Array Write Register – ITB_PTE
The ITB PTE array write register (ITB_PTE) is a write-only register through which the
ITB PTE array is written. A round-robin allocation algorithm is used. A write to the
ITB_PTE array, when retired, results in both the ITB_TAG and ITB_PTE arrays being
written. The specific entry that is written is chosen by the round-robin algorithm
described above. Figure 5–9 shows the ITB PTE array write register.
63 383743 342 20
VPTB[63:43]
SEXT(VA[47])
VA[47:13]
LK99-0012A
63 29 322 22130 0
VPTB[63:30]
VA[31:13]
LK99-0013A
63 4847 1312 0
VA[47:13]
LK99-0015A