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D–4 PALcode Restrictions and Guidelines
Alpha 21264/EV67 Hardware Reference Manual
Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
** or the PALcode, but it must be done in the manner and order below.
**
** It assumes that the retirator has been initialized, that the
** non-shadow registers are mapped, and that mapper source enables are on.
**
** Source enables are on. For fault-reset and wake from sleep, we need to
** ensure we are in the icache so we don’t fetch junk that touches the
** shadow sources before we write the destinations. For normal reset,
** we are already in the icache. However, so this macro is useful for
** all cases, force the code into the icache before doing the mapping.
**
** Assume for fault-reset, and wake from sleep case, the exc_addr is
** stored in r1.
*/
addq r31,r31,r0 /* nop*/
addq r31,r31,r0 /* nop*/
addq r31,r31,r0 /* nop*/
br r31, tch0 /* fetch in next block*/
.align 3
nxt0: lda r0,0x0086(r31) /* load I_CTL.....*/
mtpr r0,EV6__I_CTL /* .....SDE=2, IC_EN=3 (SCRBRD=4)*/
br r31, nxt1 /* continue executing in next block*/
tch0: br r31, tch1 /* fetch in next block*/
nxt1: mtpr r31,EV6__IER_CM /* clear IER_CM (SCRBRD=4) creates a map-stall
under the above mtpr to SCRBRD=4*/
addq r31,r31,r0 /* nop*/
br r31, nxt2 /* continue executing in next block*/
tch1: br r31, tch2 /* fetch in next block*/
nxt2: addq r31,r31,r0 /* 1st buffer fetch block for above map-
stall*/
addq r31,r31,r0 /* nop*/
br r31, nxt3 /* continue executing in next block*/
tch2: br r31, tch3 /* fetch in next block*/
nxt3: addq r31,r31,r0 /* 2nd buffer fetch block for above map-stall*/
addq r31,r31,r0 /* nop*/
br r31, nxt4 /* continue executing in next block*/
tch3: br r31, tch4 /* fetch in next block*/
nxt4: addq r31,r31,r0 /* need 3rd buffer fetch block to get correct
SDE bit for next fetch block*/
addq r31,r31,r0 /* nop*/
br r31, nxt5 /* continue executing in next block*/
tch4: br r31, tch5 /* fetch in next block*/
nxt5: addq r31,r31,r4 /* initialize Shadow Reg. 0*/
addq r31,r31,r5 /* initialize Shadow Reg. 1*/
br r31, nxt6 /* continue executing in next block*/
tch5: br r31, tch6 /* fetch in next block*/
nxt6: addq r31,r31,r6 /* initialize Shadow Reg. 2*/
addq r31,r31,r7 /* initialize Shadow Reg. 3*/
br r31, nxt7 /* continue executing in next block*/
tch6: br r31, tch7 /* fetch in next block*/
nxt7: addq r31,r31,r20 /* initialize Shadow Reg. 4*/