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2–18 Internal Architecture
Alpha 21264/EV67 Hardware Reference Manual
Instruction Issue Rules
2.3.2 Ebox Slotting
Instructions that are issued from the IQ, and could execute in either upper or lower
Ebox subclusters, are slotted to one pair or the other during the pipeline mapping stage
based on the instruction mixture in the fetch line. The codes that are used in Table 2–3
are as follows:
• U—The instruction only executes in an upper subcluster.
• L—The instruction only executes in a lower subcluster.
• E—The instruction could execute in either an upper or lower subcluster.
Table 2–3 defines the slotting rules. The table field Instruction Class 3, 2, 1 and 0 iden-
tifies each instruction’s location in the fetch line by the value of bits [3:2] in its PC.
ftoi FST0, FST1, L0, L1 FTOIS, FTOIT
itof L0, L1 ITOFS, ITOFF, ITOFT
mx_fpcr FM Instructions that move data from the floating-point
control register
Table 2–3 Instruction Group Definitions and Pipeline Unit
Instruction Class
3 2 1 0
Slotting
3 2 1 0
Instruction Class
3 2 1 0
Slotting
3 2 1 0
E E E E U L U L L L L L L L L L
E E E L U L U L L L L U L L L U
E E E U U L L U L L U E L L U U
E E L E U L L U L L U L L L U L
E E L L U U L L L L U U L L U U
E E L U U L L U L U E E L U L U
E E U E U L U L L U E L L U U L
E E U L U L U L L U E U L U L U
E E U U L L U U L U L E L U L U
E L E E U L U L L U L L L U L L
E L E L U L U L L U L U L U L U
E L E U U L L U L U U E L U U L
E L L E U L L U L U U L L U U L
E L L L U L L L L U U U L U U U
E L L U U L L U U E E E U L U L
E L U E U L U L U E E L U L U L
E L U L U L U L U E E U U L L U
Table 2–2 Instruction Name, Pipeline, and Types (Continued)
Class
Name Pipeline Instruction Type