Filter
Top Products
Index–10
Alpha 21264/EV67 Hardware Reference Manual
ReadBlk, 21264/EV67 command, 4–21
system probes, with
, 4–41
ReadBlkI, 21264/EV67 command
, 4–22
ReadBlkMod, 21264/EV67 command
, 4–22
system probes, with
, 4–41
ReadBlkModSpec, 21264/EV67 command
, 4–22
ReadBlkModVic, 21264/EV67 command
, 4–22
ReadBlkSpec, 21264/EV67 command
, 4–22
ReadBlkSpecI, 21264/EV67 command
, 4–22
ReadBlkVic, 21264/EV67 command
, 4–22
ReadBlkVicI, 21264/EV67 command
, 4–22
ReadBytes, 21264/EV67 command
, 4–22
ReadData, SysDc command
, 4–10, 4–11, 4–12
ReadDataDirty, SysDc command
, 4–10, 4–11, 4–12
ReadDataError, SysDc command
, 4–10, 4–11,
4–12, 4–13
ReadDataShared, SysDc command
, 4–10, 4–11,
4–12
ReadDataShared/Dirty, SysDc command
, 4–10,
4–11, 4–12
ReadLWs, 21264/EV67 command
, 4–22
ReadQWs, 21264/EV67 command
, 4–22
Register access abbreviations
, xix
Register figure conventions
, xxi
Register maps, pipelined
, 2–15
Register rename maps
, 2–6
Replay traps
, 2–31
RESET interrupt
, 6–14
Reset state machine
major operations of
, 7–1
Reset_L signal pin
, 3–5
power-on reset flow
, 7–1
RET misprediction, in PALcode
, D–15
Retire logic
, 2–8, D–1
RO,n convention
, xix
RUN reset machine state
, 7–18
RW,n convention
, xx
S
SAMPLE public instruction, B–1
Scrubbing single-bit errors
, D–19
I_CTL Ibox control register
updating I_CTL
, D–18
Second-level cache. See Bcache
Security holes
with UNPREDICTABLE results
, xxii
Serial terminal port
, 11–2
SET_DIRTY_ENABLE Cbox CSR
, 4–23, 5–39,
7–12
programming
, 4–24
SharedToDirty, 21264/EV67 command
, 4–22, 4–40
system probes, with
, 4–41
Signal name convention
, xxi
Signal pin types, defined
, 3–3
Signal pins
test
, 11–1
Single-bit error scribbing
, D–19
Single-bit errors in hardware, correcting
, 8–2
SIRR software interrupt request register
, 5–10
at power-on reset state
, 7–15
SKEWED_FILL_MODE Cbox CSR
defined
, 5–34
Sleep mode
flow
, 7–9
timing sequence, 7–11
SLEEP mode register
, 5–21
at power-on reset state
, 7–15
Spare pin type
, 3–3
SPEC_READ_ENABLE Cbox CSR
, 4–23
defined
, 5–35
SQ. See Store queue
SROM content map
, 11–6
SROM initialization
, 11–5
SROM interface, in microarchitecture
, 2–13
SROM line, Icache bit fields in a
, 11–6
SROM load
, 7–6
SROM load operation
, 11–2
SromClk_H signal pin
, 3–5, 11–2
SromData_H signal pin
, 3–5, 11–2
SromOE_L signal pin
, 3–5, 11–2
SSRAMs
dual-data rate pin assignments
, E–3
late-write non-bursting pin assignments, E–2
STC_ENABLE Cbox CSR
, 4–24
STCChangeToDirty, 21264/EV67 command
, 4–13,
4–22, 4–40
Storage temperature
, 9–1