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2–26 Internal Architecture
Alpha 21264/EV67 Hardware Reference Manual
Special Cases of Alpha Instruction Execution
Figure 2–10 Pipeline Timing for Floating-Point Load Instructions
The speculative window for floating-point load instructions is one cycle wide.
FQ-issued instructions that are issued within the speculative window of a floating-point
load instruction that has missed, are only aborted if they depend on the load being suc-
cessful.
For example, in Figure 2–10 instruction 1 is issued in the speculative window of the
load instruction.
If instruction 1 is not a user of the data returned by the load instruction, then it is
removed from the queue at its normal time (at the start of cycle 7).
If instruction 1 is dependent on the load instruction data and the load instruction hits,
instruction 1 is removed from the queue one cycle later (at the start of cycle 8). If the
load instruction misses, then instruction 1 is aborted from the Fbox pipeline and may
request service again in cycle 7.
2.7.2 Floating-Point Store Instructions
Floating-point store instructions are duplicated and loaded into both the IQ and the FQ
from the mapper. Each IQ entry contains a control bit, fpWait, that when set prevents
that entry from asserting its requests. This bit is initially set for each floating-point store
instruction that enters the IQ, unless it was the target of a replay trap. The instruction’s
FQ clone is issued when its Ra register is about to become clean, resulting in its IQ
clone’s fpWait bit being cleared and allowing the IQ clone to issue and be executed by
the Mbox. This mechanism ensures that floating-point store instructions are always
issued to the Mbox, along with the associated data, without requiring the floating-point
register dirty bits to be available within the IQ.
2.7.3 CMOV Instruction
For the 21264/EV67, the Alpha CMOV instruction has three operands, and so presents
a special case. The required operation is to move either the value in register Rb or the
value from the old physical destination register into the new destination register, based
upon the value in Ra. Since neither the mapper nor the Ebox and Fbox data paths are
otherwise required to handle three operand instructions, the CMOV instruction is
decomposed by the Ibox pipeline into two 2-operand instructions:
The Alpha architecture instruction CMOV Ra, Rb ⇒ Rc
Becomes the 21264/EV67 instructions CMOV1 Ra, oldRc ⇒ newRc1
CMOV2 newRc1, Rb ⇒ newRc2
1Cycle Number
FLD
Instruction 1
Instruction 2
2 3 4 5 6 7 8
QREDB
QR
Q
Hit
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