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Glossary–8
Alpha 21264/EV67 Hardware Reference Manual
of the clock forward logic. Additionally, the framing clock can have a period that is
less than, equal to, or greater than the time it takes to send a full four cycle command/
address.
GCLK
Global clock within the 21264/EV67.
granularity
A characteristic of storage systems that defines the amount of data that can be read and/
or written with a single instruction, or read and/or written independently.
hardware interrupt request (HIR)
An interrupt generated by a peripheral device.
high-impedance state
An electrical state of high resistance to current flow, which makes the device appear not
physically connected to the circuit.
hit
See cache hit.
Icache
Instruction cache. A cache reserved for storage of instructions. One of the three areas of
primary cache (located on the 21264/EV67) used to store instructions. The Icache con-
tains 8KB of memory space. It is a direct-mapped cache. Icache blocks, or lines, con-
tain 32 bytes of instruction stream data with associated tag as well as a 6-bit ASM field
and an 8-bit branch history field per block. Icache does not contain hardware for main-
taining cache coherency with memory and is unaffected by the invalidate bus.
IDU
A logic unit within the 21264/EV67 microprocessor that fetches, decodes, and issues
instructions. It also controls the microprocessor pipeline.
IEEE Standard 754
A set of formats and operations that apply to floating-point numbers. The formats cover
32-, 64-, and 80-bit operand sizes.
IEEE Standard 1149.1
A standard for the Test Access Port and Boundary Scan Architecture used in board-
level manufacturing test procedures.
Inf
Infinity.
INT
nn
The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data field size of nn
contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a NATU-
RALLY ALIGNED longword.