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5–2 Internal Processor Registers
Alpha 21264/EV67 Hardware Reference Manual
Instruction VA format IVA_FORM 0000 0111 5 RO 0L 3
Current mode CM 0000 1001 4 RW 0L 3
Interrupt enable IER 0000 1010 4 RW 0L 3
Interrupt enable and current mode IER_CM 0000 10xx 4 RW 0L 3
Software interrupt request SIRR 0000 1100 4 RW 0L 3
Interrupt summary ISUM 0000 1101 —RO— —
Hardware interrupt clear HW_INT_CLR 0000 1110 4 WO 0L —
Exception summary EXC_SUM 0000 1111 — RO 0L 3
PAL base address PAL_BASE 0001 0000 4 RW 0L 3
Ibox control I_CTL 0001 0001 4 RW 0L 3
Ibox status I_STAT 0001 0110 4 RW 0L 3
Icache flush IC_FLUSH 0001 0011 4 W 0L —
Icache flush ASM IC_FLUSH_ASM 0001 0010 4 WO 0L —
Clear virtual-to-physical map CLR_MAP 0001 0101 4, 5, 6, 7 WO 0L —
Sleep mode SLEEP 0001 0111 4, 5, 6, 7 WO 0L —
Process context register PCTX 01xn nnnn
1
4W0L3
Process context register PCTX 01xx xxxx 4 R 0L 3
Performance counter control PCTR_CTL 0001 0100 4 RW 0L 3
Mbox IPRs
DTB tag array write 0 DTB_TAG0 0010 0000 2, 6 WO 0L —
DTB tag array write 1 DTB_TAG1 1010 0000 1, 5 WO 1L —
DTB PTE array write 0 DTB_PTE0 0010 0001 0, 4 WO 0L —
DTB PTE array write 1 DTB_PTE1 1010 0001 3, 7 WO 0L —
DTB alternate processor mode DTB_ALTMODE 0010 0110 6 WO 1L —
DTB invalidate all process (ASM = 0) DTB_IAP 1010 0010 7 WO 1L —
DTB invalidate all DTB_IA 1010 0011 7 WO 1L —
DTB invalidate single (array 0) DTB_IS0 0010 0100 6 WO 0L —
DTB invalidate single (array 1) DTB_IS1 1010 0100 7 WO 1L —
DTB address space number 0 DTB_ASN0 0010 0101 4 WO 0L —
DTB address space number 1 DTB_ASN1 1010 0101 7 WO 1L —
Memory management status MM_STAT 0010 0111 — RO 0L 3
Mbox control M_CTL 0010 1000 6 WO 0L —
Dcache control DC_CTL 0010 1001 6 WO 0L —
Dcache status DC_STAT 0010 1010 6 RW 0L 3
Table 5–1 Internal Processor Registers (Continued)
Register Name Mnemonic
Index
(Binary)
Score-
Board
Bit Access
MT/MF
Issued
from Ebox
Pipe
Latency
for
MFPR
(Cycles)