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D–18 PALcode Restrictions and Guidelines
Alpha 21264/EV67 Hardware Reference Manual
Restriction 33 : HW_LD Physical/Lock Use
D.29 Restriction 33 : HW_LD Physical/Lock Use
The HW_LD physical/lock instruction must be one of the first three instructions in a
quad-instruction aligned fetch block. A pipeline error can occur if the HW_LD physi-
cal/lock is fetched as the fourth instruction of the fetch block.
D.30 Restriction 34 : Writing Multiple ITB Entries in the Same PAL-
code Flow
Before a PALcode flow writes multiple ITB entries, additional scoreboard bits should
be set to avoid possible corruption of the TAG IPR prior to final update in the ITB. The
addition of scoreboard bits 0 and 4 to the standard scoreboard bit 6 for ITB_TAG will
prevent subsequent HW_MTPR ITB_TAG writes from changing the staging register
TAG value prior to retirement of the HW_MTPR ITB_PTE that triggers the final ITB
update.
D.31 Guideline 35 : HW_INT_CLR Update
When writing the HW_INT_CLR IPR to clear interrupt requests, it may be necessary to
write the same value twice in distinct fetch blocks to ensure that the interrupt request is
cleared before exiting PALcode. A second write will cause a scoreboard stall until the
first write retires, creating a convenient synchronization with the PALmode exit.
D.32 Restriction 36 : Updating I_CTL[SDE]
A software interlock is required between updates of the I_CTL[SDE] and a subsequent
instruction fetch that may use any destination registers. A suggested method of ensuring
this interlock is to use two MTPR I_CTL instructions in separate fetch blocks, followed
by three more fetch blocks of non-NOP instructions.
D.33 Restriction 37 : Updating VA_CTL[VA_48]
A software interlock is required between updates of the VA_CTL[VA_48] and follow-
ing LD or ST instructions. This is necessary since the VA_CTL update will not occur
until the HW_MTPR VA_CTL instruction retires. A sufficient method of ensuring this
interlock is to write the VA_CTL with the same data in two successive fetch blocks,
causing a mapper stall. The dependant LD or ST instructions can be placed in any loca-
tion of the second fetch block.
D.34 Restriction 38 : Updating PCTR_CTL
When updating the PCTR_CTL, it may be necessary to write the update value twice. If
the counter being updated is currently disabled by way of the respective I_CTL or
PCTX bits, the value must be written twice to ensure that the counter overflow is prop-
erly cleared. The overflow bit is conditionally latched using the same write enable as
the counter update, so an additional write of the counter value will ensure that the over-
flow logic accurately reflects the addition of the new counter value plus the input condi-
tions. The new update value must not be within one cycle of overflow (within 16 for
SL0, within 4 for SL1) as required by Section D.28.