Filter
Top Products
Alpha 21264/EV67 Hardware Reference Manual
Cache and External Interfaces 4–53
Bcache Port
Table 4–46 lists the combination of control pin assertion for RAM_TYPE C.
Table 4–47 lists the combination of control pin assertion for RAM_TYPE D.
Notes:
1. The NOP condition for RAM_TYPE B is consistent with bursting nonPentium
style SSRAMs.
2. In both
RAM_TYPE A and RAM_TYPE B, the pins BcDataOE_L and BcTagOE_L
function changes from output-enable control to chip-select control.
3. In both RAM_TYPE C and RAM_TYPE D SSRAMs, the pins
BcDataOE_L and
BcTagOE_L
function as an asynchronous output enable that envelopes the Bcache
read data by providing an extra cycle of output enable.
Using these Cbox CSRs, late-write nonbursting and dual-data rate SSRAMs can be
connected to the 21264/EV67 as described in Appendix E.
4.8.4.3 BcDataInClk_H and BcTagInClk_H
The BcDataInClk_H[7:0] and BcTagInClk_H pins are used to capture tag data and
data from the Bcache data and tag RAMs respectively. Dual-data rate SSRAMs provide
a clock output with the data output pins to minimize skew between the data and clock,
thus allowing maximum bandwidth. The 21264/EV67 internally synchronizes the data
to its GCLK with clock forward receive circuitry similar to that in the system interface.
For nonDDR SSRAMs, systems can connect the Bcache data and tag output clock pins
to the Bcache data and tag input clock pins.
Table 4–46 Control Pin Assertion for RAM_TYPE C
TYPE_C NOP RA0 RA1 RA2 RA3 NOP NOP WA0 WA1 WA2 WA3 NOP
BcLoad_L HHHHH H HHHHHH
BcDataOE_L HHLLLLLHHHHH
BcDataWr_L HHHHH H HLLLLH
BcTagOE_L HLLHHHHHHHHH
BcTagWr_L HHHHH H HLHHHH
Table 4–47 Control Pin Assertion for RAM_TYPE D
TYPE_D NOP RA0 RA1 RA2 RA3 NOP NOP WA0 WA1 WA2 WA3 NOP
BcLoad_L HLHHHHHL HHHH
BcDataOE_L HHLL LLLHHHHH
BcDataWr_L HHHHHHHLLLLH
BcTagOE_L HHL LHHHHHHHH
BcTagWr_L HHHHHHHLHHHH