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6–8 Privileged Architecture Library Code
Alpha 21264/EV67 Hardware Reference Manual
Internal Processor Register Access Mechanisms
6.5.1 IPR Scoreboard Bits
In previous Alpha implementations, IPR registers were not scoreboarded in hardware.
Software was required to schedule HW_MTPR and HW_MFPR instructions for each
machine’s pipeline organization in order to ensure correct behavior. This software
scheduling task is more difficult in the 21264/EV67 because the Ibox performs
dynamic scheduling. Hence, eight extra scoreboard bits are used within the IQ to help
maintain correct IPR access order. The HW_MTPR and HW_MFPR instruction for-
mats contain an 8-bit field that is used as an IPR scoreboard bit mask to specify which
of the eight IPR scoreboard bits are to be applied to the instruction.
If any of the unmasked scoreboard bits are set when an instruction is about to enter the
IQ, then the instruction, and those behind it, are stalled outside the IQ until all the
unmasked scoreboard bits are clear and the queue does not contain any implicit or
explicit readers that were dependent on those bits when they entered the queue. When
all the unmasked scoreboard bits are clear, and the queue does not contain any of those
readers, the instruction enters the IQ and the unmasked scoreboard bits are set.
HW_MFPR instructions are stalled in the IQ until all their unmasked IPR scoreboard
bits are clear.
When scoreboard bits [3:0] and [7:4] are set, their effect on other instructions is differ-
ent, and they are cleared in a different manner.
If any of scoreboard bits [3:0] are set when a load or store instruction enters the IQ, that
load or store instruction will not be issued from the IQ until those scoreboard bits are
clear.
Scoreboard bits [3:0] are cleared when the HW_MTPR instructions that set them are
issued (or are aborted). Bits [7:4] are cleared when the HW_MTPR instructions that set
them are retired (or are aborted).
Bits [3:0] are used for the DTB_TAG and DTB_PTE register pairs within the DTB fill
flows. These bits can be used to order writes to the DTB for load and store instructions.
See Sections 5.3.1 and 6.9.1.
Bit [0] is used in both DTB and ITB fill flows to trigger, in hardware, a lightweight
memory barrier (TB-MB) to be inserted between a LD_VPTE and the corresponding
virtual-mode load instruction that missed in the TB.
6.5.2 Hardware Structure of Explicitly Written IPRs
IPRs that are written by software are physically implemented as two registers. When
the HW_MTPR instruction that writes the IPR executes, it writes its value to the first
register. When the HW_MTPR instruction is retired, the contents of the first register are
written into the second register. Instructions that either implicitly or explicitly read the
value of the IPR access the second register. Read-after-write and write-after-write
dependencies are managed using the IPR scoreboard bits. To avoid write-after-read
conflicts, the second register is not written until the writer is retired. The writer will not
be retired until the previous reader is retired, and the reader is retired after it has read its
value from the second register.
Some groups of IPRs are built using a single shared first register. To prevent write-
after-write conflicts, IPRs that share a first register also share scoreboard bits.