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E–4 21264/EV67-to-Bcache Pin Interconnections
Alpha 21264/EV67 Hardware Reference Manual
Dual-Data Rate SSRAMs
From board, pulled up to VDD TMS_H
From board, pulled up to VDD TDI_H
Unconnected or pulled down to VSS TRST_L
BcDataOE_L OE_L (G_L)
From board, pulled down to VSS SD/DD_L (B3)
Table E–5 Dual-Data Rate SSRAM Tag Pin Usage
21264/EV67 Signal Name or Board Connection Dual-Data Rate SSRAM Tag Pin Name
BcAdd_H[23:6] SA_H[17:0]
BcTag_H[33:20] DQx
BcTagOE_L LD_L (B1)
BcTagWr_L R/W_L (B2)
From board, pulled up to VDD LBO_L
From board, pulled down to VSS Q_L
SA[19:18]
BcTagInClk_H CQ_H
BcTagOutClk_H CK_H
BcTagOutClk_L CK_L
Set from board to 1/2 core voltage VREF1_H
VREF2_H
Set from board (implementation-dependent) ZQ_H
BcTagValid_H DQx
BcTagDirty_H DQx
BcTagShared_H DQx
BcTagParity_H DQx
Unconnected or terminated CQ_L
From board, pulled up to VDD TCK_H
Unconnected TDO_H
From board, pulled up to VDD TMS_H
From board, pulled up to VDD TDI_H
Unconnected TRST_L
From board, pulled down to VSS OE_L (G_L)
From board, pulled up to VDD SD/DD_L (B3)
Table E–4 Dual-Data Rate SSRAM Data Pin Usage (Continued)
21264/EV67 Signal Name or Board
Connection Dual-Data Rate SSRAM Data Pin Name