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Alpha 21264/EV67 Hardware Reference Manual
Testability and Diagnostics 11–7
Notes on IEEE 1149.1 Operation and Compliance
The instruction cache lines are loaded in the reverse order. If the fetch_count(9,0) is
zero, then, no instruction cache lines are loaded. Since the valid bits are already cleared
by the BiST operation, the first instruction fetch is missed in the instruction cache and
the chip seeks instructions from the offchip memory.
Refer to the Alpha Motherboards Software Developer’s Kit (SDK) for example C code
that calculates the predecode values of a serial Icache load.
11.6 Notes on IEEE 1149.1 Operation and Compliance
1. IEEE 1149.1 port pins on the 21264/EV67 are not pulled up or pulled down on the
chip. The necessary pull-up or pull-down function must be implemented on the
board.
2. Tms_H should not change when Trst_L is being deasserted.
References
IEEE Std. 1149.1-1993 A Test Access Port and Boundary Scan Architecture.
See Appendix B for a listing of the Boundary-Scan Register.
Table 11–3 Icache Bit Fields in an SROM Line
Fetch Bit Icache Data Fetch Bit Icache Data Fetch Bit Icache Data
0 par-MBZ 86 par-MBZ 172 lp_train
1 c[3] 87 c[0] 173:175 lp_src(2:0)
2:27 i[3](25,20,24,19,23,18,22,17
,21,16:0)
88:113 i[0](25,20,24,19,3,18,22,17,
21,16:0)
176:181 lp_idx(14:9)
28 c[2] 114 c[1] 182:186 lp_idx(8:4)
29:42 i[2](25,20,24,19,
23,18,22,17,21,16:12)
115:128 i[1] (25,20,24,19,
23,18,22,17,21,16:12)
187 lp_idx(15)
43 parity 129 parity 188:192 lp_ssp[4:0]
44:55 i[2](11:0) 130:141 i[1](11:0) ——
56 dv[3] 142 dv[0] — —
57:59 iq[3](2:0) 143:145 iq[0](2:0) — —
60:65 i[3](26:31) 146:151 i[0](26:31) — —
66,68 ea[3](2:0) 152:154 ea[0](2:0) — —
69 dv[2] 155 dv[1] — —
70,72 iq[2](2:0) 156:158 iq[1](2:0) — —
73:78 i[2](26:31) 159:164 i[1](26:31) — —
79:81 ea[2](2:0) 165:167 ea[1](2:0) — —
82:85 tr(7:4) 168:171 tr(0:3) — —