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5–14 Internal Processor Registers
Alpha 21264/EV67 Hardware Reference Manual
Ibox IPRs
Figure 5–20 Exception Summary Register
Table 5–9 describes the exception summary register fields.
Table 5–9 Exception Summary Register Fields Description
Name Extent Type Description
SEXT(SET_IOV) [63:48] RO, 0 Sign-extended value of bit 47, SET_IOV.
SET_IOV [47] RO PALcode should set FPCR[IOV].
SET_INE [46] RO PALcode should set FPCR[INE].
SET_UNF [45] RO PALcode should set FPCR[UNF].
SET_OVF [44] RO PALcode should set FPCR[OVF].
SET_DZE [43] RO PALcode should set FPCR[DZE].
SET_INV [42] RO PALcode should set FPCR[INV].
PC_OVFL [41] RO Indicates that EXC_ADDR was improperly sign extended for 48-
bit mode over/underflow IACV.
Reserved [40:14] RO, 0 Reserved for Compaq.
BAD_IVA [13] RO Bad Istream VA.
This bit should be used by the IACV PALcode routine to deter-
mine whether the offending I-stream virtual address is latched in
the EXC_ADDR register or the VA register. If BAD_IVA is clear,
EXC_ADDR contains the address; if BAD_IVA is set, VA con-
tains the address.
63 48 847 746 645 544 14 443 13 342 12 241 140 0
SEXT(SET_IOV)
SET_IOV
SET_INE
SET_UNF
SET_OVF
SET_DZE
SET_INV
PC_OVFL
BAD_IVA
REG[4:0]
INT
IOV
INE
UNF
FOV
DZE
INV
SWC
LK
99
-
00
2
6
A