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Alpha 21264/EV67 Hardware Reference Manual
Cache and External Interfaces 4–5
Physical Address Considerations
Prefetches (LDL, LDF, LDG, LDT, LDBU, LDWU) to R31 use the LDx flow, and
prefetch with modify intent (LDS) uses the STx flow. If the prefetch target is addressed
to I/O space, the upper address bit is cleared, converting the address to memory space
(PA[42:6] ). Notes follow the table.
Table 4–1 Translation of Internal References to External Interface Reference
Instruction DcHit DcW BcHit BcW Status and Action
LDx Memory 1 X X X Dcache hit, done.
LDx Memory 0 X 1 X Bcache hit, done.
LDx Memory 0 X 0 X Miss, generate RdBlk command.
LDx I/O X X X X RdBytes, RdLWs, or RdQWs based on size.
Istream Memory 1 X X X Dcache hit, Istream serviced from Dcache.
Istream Memory 0 X 1 X Bcache hit, Istream serviced from Bcache.
Istream Memory 0 X 0 X Miss, generate RdBlkI command.
STx Memory 1 1 X X Store Dcache hit and writable, done.
STx Memory 1 0 X X Store hit and not writable, set dirty flow (note 1).
STx Memory 0 X 1 1 Store Bcache hit and writable, done.
STx Memory 0 X 1 0 Store hit and not writable, set-dirty flow (note 1).
STx Memory 0 X 0 X Miss, generate RdBlkMod command.
STx I/O X X X X WrBytes, WrLWs, or WrQWs based on size.
STx_C Memory 0 X X X Fail STx_C.
STx_C Memory 1 0 X X STx_C hit and not writable, set dirty flow (note 1).
STx_C I/O X X X X Always succeed and WrQws or WrLws are generated,
based on the size.
WH64 Memory 1 1 X X Hit, done.
WH64 Memory 1 0 X X WH64 hit not writable, set dirty flow (note 1).
WH64 Memory 0 X 1 1 WH64 hit dirty, done.
WH64 Memory 0 X 1 0 WH64 hit not writable, set dirty flow (note 1).
WH64 Memory 0 X 0 X Miss, generate InvalToDirty command (note 2).
WH64 I/O X X X X NOP the instruction. WH64 is UNDEFINED for I/O
space.
ECB Memory X X X X Generate evict command (note 3).
ECB I/O X X X X NOP the instruction. ECB instruction is UNDEFINED
for I/O space.
MB/WMB
TB Fill Flows
X X X X Generate MB command (note 4). See Section 2.12.1.