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5–10 Internal Processor Registers
Alpha 21264/EV67 Hardware Reference Manual
Ibox IPRs
Figure 5–16 Interrupt Enable and Current Processor Mode Register
Table 5–5 describes the interrupt enable and current processor mode register fields.
5.2.10 Software Interrupt Request Register – SIRR
The software interrupt request register (SIRR) is a read-write register containing bits to
request software interrupts. To generate a particular software interrupt, its correspond-
ing bits in SIRR and IER[SIER] must both be set. Figure 5–17 shows the software
interrupt request register.
Table 5–5 IER_CM Register Fields Description
Name Extent Type Description
Reserved [63:39] ——
EIEN[5:0] [38:33] RW External Interrupt Enable
SLEN [32] RW Serial Line Interrupt Enable
CREN [31] RW Corrected Read Error Interrupt Enable
PCEN[1:0] [30:29] RW Performance Counter Interrupt Enables
SIEN[15:1] [28:14] RW Software Interrupt Enables
ASTEN [13] RW AST Interrupt Enable
When set, enables those AST interrupt requests that are also
enabled by the value in ASTER.
Reserved [12:5] — —
CM[1:0] [4:3] RW Current Mode
00 Kernel
01 Executive
10 Supervisor
11 User
Reserved [2:0] — —
63 39 2938 28 514 433 13 332 12 23130 0
EIEN[5:0]
SLEN
CREN
PCEN[1:0]
SIEN[15:1]
ASTEN
CM[1:0]
LK
99
-
00
22A