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Alpha 21264/EV67 Hardware Reference Manual
PALcode Restrictions and Guidelines D–21
Restriction 41: MTPR ITB_TAG, MTPR ITB_PTE Must Be in the Same Fetch Block
D.37 Restriction 41: MTPR ITB_TAG, MTPR ITB_PTE Must Be in the
Same Fetch Block
Write the ITB_TAG and ITB_PTE registers in the same fetch block. This avoids a
mispredict path write of invalid data to the ITB_TAG register.
D.38 Restriction 42: Updating VA_CTL, CC_CTL, or CC IPRs
When writing to the VA_CTL, CC_CTL, or CC IPRs, write the same value twice in dis-
tinct fetch blocks. This ensures that the instruction is retired before any mispredict from
a younger branch, DTB miss trap, or hw_ret_stall.
D.39 Restriction 43: No Trappable Instructions Along with
HW_MTPR
There are two parts to this restriction:
1. There cannot be any mispredictable/trappable instructions together with an
HW_MTPR in the current fetch block.
2. There cannot be any mispredictable/trappable instructions in the previous fetch
block.
D.40 Restriction 44: Not Applicable to the 21264/EV67
D.41 Restriction 45: No HW_JMP or JMP Instructions in PALcode
Do not include HW_JMP or JMP instructions in PALcode; use HW_RET instead.
HW_JMP always predicts in PALmode, and may mispredict to random cache blocks.
This may cause speculative code to begin executing in PALmode and may have unex-
pected side effects such as I/O stream references.
HW_RET always predicts in native mode, and when it mispredicts, it avoids specula-
tive execution in PALmode.