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6–18 Privileged Architecture Library Code
Alpha 21264/EV67 Hardware Reference Manual
Performance Counter Support
ProfileMe mode, supports a new way of statistically sampling individual instructions
during program execution. This mode counts events triggered by a targeted inflight
instruction.
Counter support uses the hardware registers listed in Table 6–9.
6.10.1 General Precautions
Initialize both counters, (PCTR_CTL[PCTR0 and PCTR1]), to zero in reset PALcode
to avoid spurious interrupts when exiting initial PALcode. Counters must be written
twice during initialization to ensure that the overflow latch has been cleared (see the
PALcode restrictions in Sections D.28 and D.34).
The counters should never be left within one cycle of overflow when disabled because
that can cause some interrupts to be blocked in anticipation of an overflow interrupt
(see PALcode restriction 32).
If a counter is at the overflow threshold and a value is written to that counter, the
counter signals an overflow interrupt upon leaving PALmode, even if that counter is
disabled. To avoid that interrupt, the PALcode should clear the interrupt by writing to
HW_INT_CLR.
Interrupts are disabled in PALmode.
As a quirk of the implementation, while counting is disabled, a read of PCTR_CTL can
yield value+some increment, where value is the actual value in PCTR_CTL, and incre-
ment for PCTR0 is in the range 0..4 (retired instructions in that cycle), and increment
for PCTR1 is dependent on SL1.
6.10.2 Aggregate Mode Programming Guidelines
Use the following information to program counters in Aggregate mode.
6.10.2.1 Aggregate Mode Precautions
Counters continue to count after overflow.
Only the counters return useful data. See Table 6–11 for counting modes.
Counters can be read by a PALcode instruction at any time to get the aggregate count.
Table 6–9 IPRs Used for Performance Counter Support
Register Name Mnemonic Relevant Fields Described in Section
ProfileMe PC PMPC All fields 5.2.6
Interrupt enable and current proces-
sor mode
IER_CM PCEN[1:0] 5.2.9
Interrupt summary ISUM PC[1:0] 5.2.11
Ibox control I_CTL SPCE, PCT0_EN, PCT1_EN 5.2.15
Ibox status I_STAT OVR, ICM, TRAP-TYPE,
LSO, TRP, MIS
5.2.16
Ibox process context PCTX PPCE 5.2.21
Performance counter support PCTR_CTL All fields 5.2.22