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Alpha 21264/EV67 Hardware Reference Manual
Glossary–15
SDRAM
Synchronous dynamic random-access memory.
second-level cache
A cache memory provided outside of the microprocessor chip, usually located on the
same module. Also called board-level, external, or module-level cache.
set-associative
A form of cache organization in which the location of a data block in main memory
constrains, but does not completely determine, its location in the cache. Set-associative
organization is a compromise between direct-mapped organization, in which data from
a given address in main memory has only one possible cache location, and fully asso-
ciative organization, in which data from anywhere in main memory can be put any-
where in the cache. An “n-way set-associative” cache allows data from a given address
in main memory to be cached in any of n locations.
SIMM
Single inline memory module.
SIP
Single inline package.
SIPP
Single inline pin package.
SMD
Surface mount device.
SNaN
Signaling NaN. See Nan.
SRAM
See SSRAM.
SROM
Serial read-only memory.
SSI
Small-scale integration.
SSRAM
Synchronous static random-access memory.
stack
An area of memory set aside for temporary data storage or for procedure and interrupt
service linkages. A stack uses the last-in/first-out concept. As items are added to
(pushed on) the stack, the stack pointer decrements. As items are retrieved from
(popped off) the stack, the stack pointer increments.