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7–10 Initialization and Configuration
Alpha 21264/EV67 Hardware Reference Manual
Energy Star Certification and Sleep Mode Flow
After the PLL has finished ramping down, the reset state machine enters the
WAIT_INTERRUPT state. Note the effects of the entry into that state on the IPRs
listed in Table 7–6.
Note that Interrupt enables are maintained during sleep mode, enabling the 21264/
EV67 to wake up. The 21264/EV67 waits for either an unmasked clock interrupt or an
unmasked device interrupt from the system.
When an enabled interrupt occurs, the PLL ramps back to full frequency. Subsequent to
that, the 21264/EV67 performs a built-in self-initialization (BiSI), a shortened built-in
self-test, which initializes the internal arrayed structures. The SROM is not reloaded.
Instead, the 21264/EV67 begins fetching code from the system at address PAL_BASE
+ 0x780.
Figure 7–3 shows the sleep mode sequence of operations. In Figure 7–3, note the fol-
lowing constraint and informational symbols:
Constraints:
Informational symbols:
Table 7–6 Effect on IPRs After Transition Through Sleep Mode
IPR Effects After Transition Through Sleep Mode
PAL_BASE Maintained (not reset)
I_CTL Bit value = 3 (both Icaches are enabled)
PCTX[FPE] Set
WRITE_MANY Cleared (That is, the WRITE_MANY chain is initialized and the Bcache is
turned off.)
AMin = 1 FrameClk_x cycle
a Approximately 525 GCLK cycles for external framing clock to be sampled and captured
bNext FrameClk_x rising edge
c1 FrameClk_x cycle
d3 FrameClk_x cycles
e Approximately 264 GCLK cycles to prevent first command from appearing too early
f Approximately 8192 GCLK cycles for BiSI
g 16 GCLK cycles