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2–12 Internal Architecture
Alpha 21264/EV67 Hardware Reference Manual
21264/EV67 Microarchitecture
• Virtual tag bits [47:15]
• 8-bit address space number (ASN) field
• 1-bit address space match (ASM) bit
• 1-bit PALcode bit to indicate physical addressing
• Valid bit
• Data and tag parity bits
• Four access-check bits for the following modes: kernel, executive, supervisor, and
user (KESU)
• Additional predecoded information to assist with instruction processing and fetch
control
2.1.5.2 Data Cache
The data cache (Dcache) is a 64KB, 2-way set-associative, virtually indexed, physically
tagged, write-back, read/write allocate cache with 64-byte blocks. During each cycle
the Dcache can perform one of the following transactions:
• Two quadword (or shorter) read transactions to arbitrary addresses
• Two quadword write transactions to the same aligned octaword
• Two non-overlapping less-than-quadword writes to the same aligned quadword
• One sequential read and write transaction from and to the same aligned octaword
Each Dcache block contains:
• 64 data bytes and associated quadword ECC bits
• Physical tag bits
• Valid, dirty, shared, and modified bits
• Tag parity bit calculated across the tag, dirty, shared, and modified bits
• One bit to control round-robin set allocation (one bit per two cache blocks)
The Dcache contains two sets, each with 512 rows containing 64-byte blocks per row
(that is, 32K bytes of data per set). The 21264/EV67 requires two additional bits of vir-
tual address beyond the bits that specify an 8KB page, in order to specify a Dcache row
index. A given virtual address might be found in four unique locations in the Dcache,
depending on the virtual-to-physical translation for those two bits. The 21264/EV67
prevents this aliasing by keeping only one of the four possible translated addresses in
the cache at any time.
2.1.6 Memory Reference Unit
The memory reference unit (Mbox) controls the Dcache and ensures architecturally
correct behavior for load and store instructions. The Mbox contains the following struc-
tures:
• Load queue (LQ)
• Store queue (SQ)