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Alpha 21264/EV67 Hardware Reference Manual
Internal Processor Registers 5–13
Ibox IPRs
Table 5–8 describes the hardware interrupt clear register fields.
5.2.13 Exception Summary Register – EXC_SUM
The exception summary register (EXC_SUM) is a read-only register that contains
information about instructions that have triggered traps. The register is updated at trap
delivery time. Its contents are valid only if it is read (by way of a HW_MFPR) in the
first fetch block of the exception handler. There are three types of traps for which this
register captures related information:
• Arithmetic traps: The instruction generated an exceptional condition that should be
reported to the operating system, and/or the FPCR status bit associated with this
condition is clear and should be set by PALcode. Additionally, the REG field con-
tains the register number of the destination specifier for the instruction that trig-
gered the trap.
• Istream ACV: The BAD_IVA bit of this register indicates whether the offending
Istream virtual address is latched into the EXC_ADDR register or the VA register.
• Dstream exceptions: The REG field contains the register number of either the
source specifier (for stores) or the destination specifier (for loads) of the instruction
that triggered the trap.
Figure 5–20 shows the exception summary register.
Table 5–8 Hardware Interrupt Clear Register Fields Description
Name Extent Type Description
Reserved [63:33] ——
SL [32] W1C Clears serial line interrupt request
CR [31] W1C Clears corrected read error interrupt request
PC[1:0] [30:29] W1C Clears performance counter interrupt requests
MCHK_D [28] W1C Clears Dstream machine check interrupt request
Reserved [27] — —
FBTP [26] W1S Forces the next Bcache hit that fills the Icache to generate bad
Icache fill parity
Reserved [25:0] — —