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D–8 PALcode Restrictions and Guidelines
Alpha 21264/EV67 Hardware Reference Manual
Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group
br r31,palbase_init
palbase_init:
br r0, br60 /* r0 <- current location */
br60: lda r1, (EntryPoint-br60)(r0) /* r1 <- location of codebase */
mtpr r1, EV6__PAL_BASE /* set up pal_base register */
bis r31, 2, r0
mtpr r0, EV6__VA_CTL
bis r31, 8, r0
mtpr r0, EV6__M_CTL
br r0, jmp0
jmp0: addq r0, (jmp1-jmp0+1), r0
hw_rets/jmp(r0)
jmp1:
lda r1, 1(r31) /* r1 <- cc_ctl enable bit */
sll r1, 32, r1
mtpr r1, EV6__CC_CTL /* Enable/clear the cycle counter. */
/*
** Now initialize the dcache to allow the
** minidebugger so save gpr’s
*/
D.2 Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard
Group
For convenience of implementation, only one explicit writer (HW_MTPR) to IPRs that
are in the same group can appear in the same fetch block (octaword-aligned octaword).
Multiple explicit writers to IPRs that are not in the same scoreboard group can appear.
If this restriction is violated, the IPR readers might not see the in-order state. Also, the
IPR might ultimately end up with a bad value.
D.3 Restriction 4 : No Writers and Readers to IPRs in Same Score-
board Group
This restriction is made for the convenience of microprocessor implementation.
An explicit reader of an IPR in a particular scoreboard group cannot follow an explicit
writer (HW_MTPR) to an IPR in that same scoreboard group within one fetch block
(octaword-aligned octaword). Also within one fetch block, an implicit reader of an IPR
in a particular scoreboard group cannot follow an explicit writer (HW_MTPR) to an
IPR in that scoreboard group. This restriction covers writes to DTB_PTE or DTB_TAG
followed by LD, ST, or any memory operation, including all types of JMP instructions
and HW_RET instructions that do not have the STALL bit set.