Filter
Top Products
Alpha 21264/EV67 Hardware Reference Manual
Internal Architecture 2–39
Design Examples
2.16 Design Examples
The 21264/EV67 can be designed into many different uniprocessor and multiprocessor
system configurations. Figures 2–12 and 2–13 illustrate two possible configurations.
These configurations employ additional system/memory controller chipsets.
Figure 2–12 shows a typical uniprocessor system with a second-level cache. This sys-
tem configuration could be used in standalone or networked workstations.
Figure 2–12 Typical Uniprocessor Configuration
Figure 2–13 shows a typical multiprocessor system, each processor with a second-level
cache. Each interface controller must employ a duplicate tag store to maintain cache
coherency. This system configuration could be used in a networked database server
application.
21264
Tag
Address
Out
Address
Address
In
Data
Data
L2 Cache
Tag
Store
Data
Store
21272 Core
Logic Chipset
Data Slice
Chips
Control
Chips
Host PCI
Bridge Chip
Duplicate
Tag Store
(Optional)
DRAM
Arrays
Address
Data
64-bit PCI Bus
FM-05573-EV67