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2–36 Internal Architecture
Alpha 21264/EV67 Hardware Reference Manual
Performance Measurement Support—Performance Counters
2.13 Performance Measurement Support—Performance Counters
The 21264/EV67 provides hardware support for two methods of obtaining program
performance feedback information. The two methods do not require program modifica-
tion. The first method offers similar capabilities to earlier microprocessor performance
counters. The second method supports the new ProfileMe way of statistically sampling
individual instructions during program execution to develop a model of program execu-
tion. Both methods use the same hardware registers.
See Section 6.10 for information about counter control.
2.14 Floating-Point Control Register
The floating-point control register (FPCR) is shown in Figure 2–11.
Figure 2–11 Floating-Point Control Register
The floating-point control register fields are described in Table 2–14.
Table 2–14 Floating-Point Control Register Fields
Name Extent Type Description
SUM [63] RW Summary bit. Records bit-wise OR of FPCR exception bits.
INED [62] RW Inexact Disable. If this bit is set and a floating-point instruction that enables
trapping on inexact results generates an inexact value, the result is placed in the
destination register and the trap is suppressed.
636261 6059 4958 4857 47565554535251 50 0
SUM
INED
UNFD
UNDZ
DYN
IOV
INE
UNF
OVF
DZE
INV
OVFD
DZED
INVD
DNZ
LK
99
-
0050
A