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3–8 Hardware Interface
Alpha 21264/EV67 Hardware Reference Manual
Pin Assignments
3.3 Pin Assignments
The 21264/EV67 package has 587 pins aligned in a pin grid array (PGA) design. There
are 380 functional signal pins, 1 dedicated 3.3-V pin for the PLL, 112 ground VSS pins,
and 94 VDD pins. Table 3–4 lists the signal pins and their corresponding pin grid array
(PGA) locations in alphabetical order for the signal type. Table 3–5 lists the pin grid
array locations in alphabetical order
Reset_L I_DA 1 System reset. This signal protects the 21264/EV67 from dam-
age during initial power-up. It must be asserted until
DCOK_H is asserted. After that, it is deasserted and the
21264/EV67 begins its reset sequence.
SromClk_H O_OD_TP 1 Serial ROM clock.
SromData_H I_DA 1 Serial ROM data.
SromOE_L O_OD_TP 1 Serial ROM enable.
Tck_H I_DA 1 IEEE 1149.1 test clock.
Tdi_H I_DA 1 IEEE 1149.1 test data-in signal.
Tdo_H O_OD_TP 1 IEEE 1149.1 test data-out signal.
TestStat_H O_OD_TP 1 Test status pin.
Tms_H I_DA 1 IEEE 1149.1 test mode select signal.
Trst_L I_DA 1 IEEE 1149.1 test access port (TAP) reset signal.
Table 3–4 Pin List Sorted by Signal Name
Signal Name PGA Location Signal Name PGA Location Signal Name PGA Location
BcAdd_H_10 B30 BcAdd_H_11 D30 BcAdd_H_12 C31
BcAdd_H_13 H28 BcAdd_H_14 G29 BcAdd_H_15 A33
BcAdd_H_16 E31 BcAdd_H_17 D32 BcAdd_H_18 B34
BcAdd_H_19 A35 BcAdd_H_20 B36 BcAdd_H_21 H30
BcAdd_H_22 C35 BcAdd_H_23 E33 BcAdd_H_4 B28
BcAdd_H_5 E27 BcAdd_H_6 A29 BcAdd_H_7 G27
BcAdd_H_8 C29 BcAdd_H_9 F28 BcCheck_H_0 F2
BcCheck_H_1 AB4 BcCheck_H_10 AW1 BcCheck_H_11 BD10
BcCheck_H_12 E45 BcCheck_H_13 AC45 BcCheck_H_14 AT4 4
BcCheck_H_15 BB36 BcCheck_H_2 AT 2 BcCheck_H_3 BC11
BcCheck_H_4 M38 BcCheck_H_5 AB42 BcCheck_H_6 AU43
BcCheck_H_7 BC37 BcCheck_H_8 M8 BcCheck_H_9 AA3
BcData_H_0 B10 BcData_H_1 D10 BcData_H_10 L3
BcData_H_100 D42 BcData_H_101 D44 BcData_H_102 H40
BcData_H_103 H42 BcData_H_104 G45 BcData_H_105 L43
Table 3–3 21264/EV67 Signal Descriptions by Function (Continued)
Signal Type Count Description