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Glossary–16
Alpha 21264/EV67 Hardware Reference Manual
STRAM
Self-timed random-access memory.
superpipelined
Describes a pipelined machine that has a larger number of pipe stages and more com-
plex scheduling and control. See also pipeline.
superscalar
Describes a machine architecture that allows multiple independent instructions to be
issued in parallel during a given clock cycle.
system clock
The primary skew controlled clock used throughout the interface components to clock
transfer between ASICs, main memory, and I/O bridges.
tag
The part of a cache block that holds the address information used to determine if a
memory operation is a hit or a miss on that cache block.
target clock
Skew controlled clock that receives the output of the RECEIVE MUX.
TB
Translation buffer.
tristate
Refers to a bused line that has three states: high, low, and high-impedance.
TTL
Transistor-transistor logic.
UART
Universal asynchronous receiver-transmitter.
UNALIGNED
A datum of size 2**N stored at a byte address that is not a multiple of 2**N.
unconditional branch instructions
Instructions that change the flow of program control without regard to any condition.
Contrast with conditional branch instructions.
UNDEFINED
An operation that may halt the processor or cause it to lose information. Only privileged
software (that is, software running in kernel mode) can trigger an UNDEFINED opera-
tion. (This meaning only applies when the word is written in all upper case.)