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Alpha 21264/EV67 Hardware Reference Manual
Traps
load-load order
, 2–32
Mbox order
, 2–31
replay, 2–31
store-load order, 2–32
Trst_L signal pin
, 3–6
U
UNALIGN fault, 6–13
Unaligned convention
, xx
V
VA virtual address register, 5–4
at power-on reset state
, 7–15
VA_CTL virtual address control register
, 5–4
at power-on reset state
, 7–15
updating VA_48 field, D–18
VA_FORM virtual address format register
, 5–5
at power-on reset state
, 7–15
VAF. See Victim address file
VAX floating-point instruction opcodes
, A–11
VBIAS defined
, 9–2
VDB. See Victim data buffer
VDBFlushRequest, 21264/EV67 command
, 4–21
VDD signal pin list
, 3–16
VDD, values for
, 9–3
VDF. See Victim data file
Vdiff defined
, 9–2
Victim address file
described
, 2–11
Victim address file, described
, 2–11
Victim data buffer (VDB)
, 4–8
Virtual address support
, 1–2
Virtual program counter logic
, 2–2
VPC. See Virtual program counter logic
VREF, values for
, 9–3
VSS signal pin list
, 3–16
W
WAIT_BiSI reset machine state, 7–18
WAIT_BiST reset machine state
, 7–18
WAIT_ClkFwdRst0 reset machine state
, 7–18
WAIT_ClkFwdRst1 reset machine state
, 7–18
WAIT_INTERRUPT reset machine state
, 7–19
WAIT_NOMINAL reset machine state
, 7–17
WAIT_RESET reset machine state
, 7–18
WAIT_SETTLE reset machine state
, 7–17
WAKEUP interrupt
, 6–14
WAR, eliminating
, 2–6
Warm reset flow
, 7–11
WAW
eliminating
, 2–6
WMB instruction processing
, 2–34
WO,n convention
, xx
Wrap order
double-pumped
, 4–38
interleaved, 4–37
WrBytes, 21264/EV67 command
, 4–22, 4–39
Write hint instructions, translation to external
interface
, 4–5
WRITE_MANY chain
, 5–38
example
, 5–39
values for Bcache initialization, 7–12
WRITE_MANY register
after fault reset
, 7–8
after warm reset
, 7–11
through sleep mode, 7–10
WRITE_ONCE chain description
, 5–33
Write-after-read. See WAR
Write-after-write. See WAW
WrLWs, 21264/EV67 command
, 4–22, 4–39
WrQWs, 21264/EV67 command
, 4–22, 4–39
WrVictimBlk, 21264/EV67 command
, 4–22, 4–39
system probes, with
, 4–41
X
X convention, xxi