Filter
Top Products
Alpha 21264/EV67 Hardware Reference Manual
Index–7
2–16
Integer execution unit. See Ebox
Integer issue queue
, 2–6
pipelined
, 2–15
Internal processor registers
, 5–1
accessing
, 6–7
explicitly written, 6–8
implicitly written, 6–9
ordering access
, 6–9
paired fetch order, 6–9
scoreboard bits for, 6–8
INTERRUPT interrupt
, 6–14
INVAL_TO_DIRTY Cbox CSR
, 4–23
programming
, 4–23
INVAL_TO_DIRTY_ENABLE Cbox CSR
, 5–39,
7–12
InvalToDirty, 21264/EV67 command
, 4–12, 4–22,
4–40
system probes, with
, 4–41
InvalToDirtyVic, 21264/EV67 command
, 4–22,
4–40
IOWB. See I/O write buffer
IPRs. See Internal processor registers
IQ. See Integer issue queue
IRQ_H signal pins
, 3–5
Istream
, 2–5
Istream memory references
translation to external references
, 4–5
ISTREAM_BC_DBL error status in C_STAT
, 5–41
ISTREAM_BC_ERR error status in C_STAT
, 5–41
ISTREAM_MEM_DBL error status in C_STAT
,
5–41
ISTREAM_MEM_ERR error status in C_STAT
,
5–41
ISUM interrupt summary register
, 5–11
at power-on reset state
, 7–15
ITB
, 2–5
ITB fill
, 6–16
ITB miss, pipeline abort delay with
, 2–16
ITB_IA invalidate-all register
, 5–7
at power-on reset state
, 7–15
ITB_IAP invalidate-all (ASM=0) register
, 5–7
at power-on reset state
, 7–15
ITB_IS invalidate single register
, 5–7
at power-on reset state
, 7–15
ITB_MISS fault
, 6–14
ITB_PTE array write register
, 5–6
at power-on reset state
, 7–14
ITB_TAG array write register
, 5–6
at power-on reset state
, 7–14
IVA_FORM instruction virtual address format
register
, 5–9
at power-on reset state
, 7–15
J
JITTER_CMD Cbox CSR, defined, 5–38
JMP misprediction, in PALcode
, D–15
JSR misprediction
in PALcode
, D–15
pipeline abort delay with, 2–16
JSR_COR misprediction, in PALcode
, D–15
Junction temperature
, 9–1
L
Late-write non-bursting SSRAM pin assignments,
E–2
LDBU instruction, normal prefetch with
, 2–23
LDF instruction, normal prefetch with
, 2–23
LDG instruction, normal prefetch with
, 2–23
LDQ instruction, prefetch with evict next
, 2–24
LDS instruction, prefetch with modify intent
, 2–23
LDT instruction, normal prefetch with
, 2–23
LDWU instruction, normal prefetch with
, 2–23
LDx_L instructions
in-order processing for
, 4–15
locking mechanism for
, 4–14
Load hit speculation
, 2–24
Load instructions
ECC with
, 8–3
I/O reference ordering, 2–31
Mbox order traps
, 2–31
memory reference ordering, 2–31
translation to external interface, 4–5
Load queue, described
, 2–13
Load-load order trap
, 2–32
Local predictor
, 2–4
Lock mechanism
, 4–14
Logic symbol, the 21264/EV67
, 3–2
LQ. See Load queue
M
M_CTL Mbox control register, 5–29
at power-on reset state
, 7–16
MAF. See Miss address file
MB instruction processing
, 2–33