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Intel
®
820E Chipset
R
Design Guide 151
Figure 76. Test Load vs. Actual System Load
V
TT
Q
Q
SET
CLR
D
Vcc
CLK
R
TEST
Test load
Driver pin
Driver pad
T
REF
T
CO
I/O Buffer
Q
Q
SET
CLR
D
Vcc
CLK
Driver pad
T
FLIGHTSYSTEM
I/O Buffer
V
TT
R
TT
Actual system load
Receiver pin
test_actual_load
The previous figure shows the different configurations for T
CO
testing and flight time simulation. The
flip-flop represents the logic input and driver stage of a typical AGTL+ I/O buffer. T
CO
timings are
specified at the driver pin output. T
FLIGHT-SYSTEM
usually is reported by a simulation tool as the time from
the driver pad starting its transition to the time when the receiver’s input pin sees a valid data input. Since
both timing numbers (T
CO
, T
FLIGHT-SYSTEM
) include propagation time from the pad to the pin, it is
necessary to subtract this time (T
REF
) from the reported flight time to avoid double counting. T
REF
is
defined as the time required for the driver output pin to reach the measurement voltage, V
REF
, starting
from the beginning of the driver transition at the pad. T
REF
must be generated using the same test load for
T
CO
. Intel provides this timing value in the AGTL+ I/O buffer models.
In this manner, the following valid delay equation is satisfied:
Equation 8. Valid Delay Equation
Valid delay = T
CO
+ T
FLIGHT-SYS
– T
REF
= T
CO-MEASURED
+ T
FLIGHT-MEASURED
This valid delay equation yields the total time from when the driver sees a valid clock pulse to the time
when the receiver sees a valid data input.
3.2.6.3. Flight Time Hardware Validation
When a measurement is made in the actual system, T
CO
and flight time do not need T
REF
correction since
these are the actual numbers. These measurements include all of the effects pertaining to the
driver-system interface, and the same is true for T
CO
. Therefore, the sum of the measured T
CO
and the
measured flight time must be equal the valid delay calculated previously.