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Intel
®
820E Chipset
R
6 Design Guide
3.2.3.
Pre-Layout Simulation................................................................................145
3.2.3.1. Methodology..................................................................................145
3.2.3.2. Sensitivity Analysis........................................................................145
3.2.3.3. Monte Carlo Analysis ....................................................................146
3.2.3.4. Simulation Criteria.........................................................................146
3.2.4. Place and Route Board..............................................................................147
3.2.4.1. Estimate Component-to-Component Spacing for AGTL+ Signals 147
3.2.4.2. Layout and Route Board ...............................................................147
3.2.4.3. Host Clock Routing .......................................................................148
3.2.4.4. APIC Data Bus Routing.................................................................148
3.2.5. Post-Layout Simulation..............................................................................149
3.2.5.1. Intersymbol Interference ...............................................................149
3.2.5.2. Crosstalk Analysis.........................................................................150
3.2.5.3. Monte Carlo Analysis ....................................................................150
3.2.6. Validation ...................................................................................................150
3.2.6.1. Measurements ..............................................................................150
3.2.6.2. Flight Time Simulation...................................................................150
3.2.6.3. Flight Time Hardware Validation...................................................151
3.3. Theory..........................................................................................................................152
3.3.1. AGTL+ ......................................................................................................152
3.3.2. Timing Requirements.................................................................................152
3.3.3. Crosstalk Theory........................................................................................153
3.3.3.1. Potential Termination Crosstalk Problems....................................154
3.4. More Details and Insight ..............................................................................................155
3.4.1. Textbook Timing Equations .......................................................................155
3.4.2. Effective Impedance and Tolerance/Variation...........................................156
3.4.3. Power/Reference Planes, PCB Stack-Up, and High-Frequency
Decoupling .................................................................................................156
3.4.3.1. Power Distribution .........................................................................156
3.4.3.2. Reference Planes and PCB Stack-Up ..........................................157
3.4.3.3. High-Frequency Decoupling..........................................................159
3.4.4. Clock Routing ............................................................................................160
3.5. Definitions of Flight Time Measurements/Corrections and Signal Quality...................160
3.5.1. V
REF
Guard Band .......................................................................................161
3.5.2. Ringback Levels ........................................................................................161
3.5.3. Overdrive Region.......................................................................................161
3.5.4. Flight Time Definition and Measurement...................................................162
3.6. Conclusion ...................................................................................................................162
4. Clocking....................................................................................................................................163
4.1. Clock Generation .........................................................................................................163
4.2. Component Placement and Interconnection Layout Requirements ............................168
4.2.1. 14.318 MHz Crystal to CK133 ...................................................................168
4.2.2. CK133 to DRCG ........................................................................................168
4.2.3. MCH to DRCG ...........................................................................................169
4.2.4. DRCG-to-RDRAM Channel .......................................................................170
4.2.5. Trace Length..............................................................................................170
4.3. DRCG Impedance Matching Circuit.............................................................................172
4.3.1. DRCG Layout Example..............................................................................173
4.4. AGP Clock Routing Guidelines ....................................................................................173
4.5. Clock Routing Guidelines for Intel
®
PGA370 Designs..................................................173
4.6. Series Termination Resistors for CK133 Clock Outputs..............................................173
4.7. Unused Outputs ...........................................................................................................174