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3-20-2000_14:02
CLOCK SYNTHESIZER
5
JP20
10K
R230
C364
82PF
4,7
SEL133/100#
4PF
C363
CK133_XIN
SIO_14MHZ_R
IHC_14MHZ_R
IHC_48MHZ_R
TEST_CLK66_R
ICH_CLK66_R
MCH_CLK66_R
SIO_PCLK7_R
FWHPCLK_R
PCLK5_R
PCLK4_R
PCLK3_R
PCLK2_R
PCLK1_R
ICHPCLK_R
ITPCLK_R
CK133_XOUT
VCC_3_3_CK133_FB
PCISTOP#
CPUSTOP#
CK133_PWRDWN#
SPREAD#
SEL0
VCC2_5_CK133_FB
APICCLK_R
PICCLK_R
33
R211
PCLK5
10K
R206
10K
R203
JP15
7
HCLKOUT
7
RCLKOUT
25
PCLK1
CPUHCLK
4
MCHCLK
6
14.318MHZ
Y3
21
22
R188
33
R165
33
R169
33
R186
33
R191
33
R183
26
PCLK3
26
PCLK4
10
FWHPCLK
9
ICH_14MHZ
R147
22
12
SIO_PCLK7
AGPCLK_CONN
24
R195
33
7
MCH_CLK66
22
R221
R200
51-1%51-1%
R185
9
ICH_48MHZ
33
R194
10K
R202
8
MULT0_GPIO
JP17
R196
10K
R192
10K
33
R201
33
R187
FBHS01L
L20
21
L21
FBHS01L
12
22
R155
R170
30
9
ICH_CLK66
R150
22
8
ICHPCLK
25
PCLK2
DRCG_CLK
DRCG_CLKB#
R205
39-1%
R182
39-1%
CLKTM_RD
0.1UF
C207
0.1UF
C215 C223
0.1UF
0.1UF
C186
0.1UF
C198
0.1UF
C206
0.1UF
C214
10PF
C185
10PF
C189
0.1UF
C199
0.1UF
C192
0.1UF
C190
0.1UF
C180
C204
0.1UF
0.1UF
C220
10UF
C209
0.1UF
C196
10UF
C171
10UF
C170
33
R210
12
SIO_14MHZ
R199
10K
R224
220
R197
10K
STOPB#
10K
R219
10K
R204
MULT0
DRCG_PWRDWN#
R156
22
CPU_DIV2_1_R
R148
22
4
ITPCLK
33
R164
CPU_DIV2
JP14
SEL1
VCC3_3_DRCG_FB
FBHS01L
L22
12
11
CLKTM#
11
CLKTM
C208
0.1UF
U11
5
55
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
4
3
2
1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
56
DRCG+
U12
21
17
2
12
11
24
23
22
20
18
16
15
14
10
7
6
9
8
5
4
3
1
13
0.1UF
C205
4
APICCLK_CPU
8
APICCLK_ICH
33
R220
CPUCLK3_R
CPUHCLK_R
R151
30
CPU_DIV2_2_R
30
R166
APIC2_R
33
R189
10PF
C476
10PF
C477
33
R184
JP13
3
2
1
JP19
JP26
1
2
3
8
DRCG_CTRL
9
MULT1_GPIO
R217
10K
MULT1
TEST_CLK66
VCC3_3
DRAWN BY:
LAST REVISED: SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87 6 54 32 1
A
B
C
D
12345678
D
C
B
A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE Camino2
VCC3_3
VCC3_3
XTAL
VCC3_3
VCC2_5
VCC2_5
VCC3_3
VCC1_8
VCC1_8
2_5V
CK133
VDD25V_1
APIC1
APIC0
VSS7
VDD25V_2
CPU_DIV2_1
CPU_DIV2_2
VSS8
VDD25V_3
CPUCLK3
CPUCLK2
VSS9
VDD25V_4
CPUCLK1
CPUCLK0
VSS10
VDD3V_6
VSS11
CPUSTOP#
PWRDWN#
SPREAD#
SEL1
SEL0
VDD3V_7
VSS1
REF0
REF1
VDD3V_1
XTAL_OUT
VSS2
PCICLK_F
PCICLK1
VDD3V_2
PCICLK2
PCICLK3
VSS3
PCICLK4
PCICLK5
VDD3V_3
PCICLK6
PCICLK7
VSS4
VSS5
3V66_0
3V66_1
VDD3V_4
VSS6
3V66_2
3V66_3
VDD3V_5
VSS12
48MHZ
APIC2
XTAL_IN
SEL133/100#
PCISTOP#
GND
VDDIR
VDDP
GNDP
GNDI
GNDC
VDDC
PCLKM
VDDIPD
MULT1
MULT0
VDDO1
CLKB#
CLK
VDDO2
S1
S0
STOPB#
PWRDN#
REFCLK
GNDO1
GNDO2
SYNCLKN
19
NC
VCC3_3
Place C364 next to VDDP
JP19 is for debug only. CLKTM and CLKTM# RC network must use 5% or better tolerance components.
All jumpers may not be required, but are included for test purposes.
for debug.
Provide at least one 0.1uF decoupling cap per power pin.
VDDIR pin on DRCG should be decoupled at the component with a 0.1uF cap.
Keep stubs on unused outputs as short as possible.
Tie CPUCLK and MCHCLK outputs together.
Clock Synthesizer
No stuff C363
No stuff R220
JP13 is for debug only.
SEL133/100# JP15 JP17 Function
0 IN IN All outputs Tri-State
0 IN OUT Reserved
0 OUT IN Active 100MHz, 48MHz PLL inactive
0 OUT OUT Active 100MHz, 48MHz PLL active
1ININTest Mode
1 IN OUT Reserved
1 OUT IN Active 133MHz,48MHz PLL inactive
1 OUT OUT Active 133MHz,48MHz PLL active*
Sprd Spect JP14
Enabled* IN
Disabled OUT
HOST
BUS/RAMBUS
JP13
100/400 OUT
133/400 2-3