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Intel
®
820E Chipset
R
Design Guide 173
4.3.1. DRCG Layout Example
Figure 95. DRCG Layout Example
Rs - 39
Ω
(Keep trace from DRCG to
Rs VERY short)
Rp - 51
Ω
(Keep trace from Rs
to Rp short)
CTM/CTM# route on
bottom layer
Cmid - 100pF
EMI Cap - 4pF
Do Not Stuff
Decoupling Cap - 0.1uF
(Place VERY Near DRCG 3.3V Pin!)
Decoupling Cap - 0.1uF
(Place VERY Near DRCG 3.3V Pin!)
Decoupling Cap - 0.1uF
(Place VERY Near DRCG 3.3V Pin!)
Decoupling Cap - 0.1uF
(Place VERY Near DRCG 3.3V Pin!)
Bulk Decoupling Cap - 10uF
(Place Near DRCG)
Ferrite Bead
(L22 in Reference Schematics)
3.3V-DRCG Flood
Flood 3.3V-DRCG on the top layer
around DRCG. Flood MUST include:
4 DRCG Power Pins
4 0.1uF Capacitors
1 10uF Bulk Capacitor
1 Isolation Ferrite Bead
4.4. AGP Clock Routing Guidelines
The AGP clock must be routed with 20 mil spacing to all other signals, and it must meet the length
guidelines in Figure 87.
4.5. Clock Routing Guidelines for Intel
®
PGA370 Designs
For the Intel 820E chipset/FC-PGA clock routing guidelines, refer to the Intel
®
820 Chipset Design
Guide Addendum for the Intel
®
Pentium
®
III Processor for the PGA370 Socket. These guidelines can be
downloaded from the Intel website at http://developer.intel.com/design/chipsets/designex/298178.htm
.
4.6. Series Termination Resistors for CK133 Clock Outputs
All used outputs require series termination resistors. The recommended resistor values are defined by
simulations. The stub length to the CK133 of these resistors can be compromised to make room for
decoupling caps. As a rule, keep all resistor stubs within 250 mils of the CK133. If routing rules allow,
Rpacks can be used, if power dissipation is not exceeded for the Rpack.