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Intel
®
820E Chipset
R
Design Guide 61
Signal Groups
• 1× timing domain
CLK (3.3 V)
RBF#
WBF#
ST[2:0]
PIPE#
REQ#
GNT#
PAR
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
• 2×/4× timing domains
Set 1
AD[15:0]
C/BE[1:0]#
AD_STB0
AD_STB0# (used in 4× mode only)
Set 2
AD[31:16]
C/BE[3:2]#
AD_STB1
AD_STB1# (used in 4× mode only)
Set 3
SBA[7:0]
SB_STB
SB_STB# (used in 4× mode only)
• Miscellaneous, async
USB+
USB-
OVRCNT#
PME#
TYPDET#
PERR#
SERR#
INTA#
INTB#