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3-20-2000_10:15 14
AUDIO
LNLVL_L_R
13
LNLVL_OUT_L
R2
20K
R4
20K U1
8
7
6
5
1
2
3
4
13
MIC_IN
4.7K
R30
4.7K
R51
4.7K
R27
4.7K
R52
13
CD_R
13
CD_L
13
CD_REF
R18
4.7K
R25
4.7K
LINE_IN_R
13
LINE_IN_L
13
1K
R9
2.2K
R7
13VCC5_AUDIO
13
LNLVL_OUT_R
L5
21
L1
21
L4
12
MIC_IN_R MIC_IN_FB
LINE_IN_R_C
LINE_IN_L_C LINE_IN_L_FB
R1
20K
R3
20K
LNLVL_R_C
LNLVL_L_C
LNLVL_R_R
HP_OUTA
HP_OUTB
HP_OUTA_C
HP_OUTB_C
HP_OUTA_FB
HP_OUTB_FB
MIC_IN_C
13
AUD_VREFOUT
AC_BYPASS
L2
21
L3
12
LINE_IN_R_FB
J5
LI25
LI23
LI24
LI22
LI21
J5
M16
M17
M19
M18
M20
CD_REF_J
CD_L_C
CD_REF_C
CD_R_C
J4
1
2
3
4
CD_L_J
CD_R_J
13EAPD
C23
1UF-TANT
12
1UF
C58
12
1UF
C59
21
C50
1UF
12
C13
1UF-TANT
21
C2
1UF
21
100UF
C10
21
C3
100UF
12
10PF-NPO
C24
12
C11
10PF-NPO
21
C6
1UF-TANT
12
0.01UF
C34
10PF-NPO
C28
21
C27
1UF-TANT
21
C26
10PF-NPO
12
10PF-NPO
C22
21
C25
1UF-TANT
21
100PF
C4
100PF
C8
J5
HP30
HP28
HP29
HP27
HP26
C14
0.1UF
12
DRAWN BY:
LAST REVISED: SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87 6 54 32 1
A
B
C
D
12345678
D
C
B
A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE Camino2
AGND
AGND
LM4880
OUTA
INA
BYPASS
GND
VDD
OUTB
INB
SHUTDN
AGND AGND
AGND
AGND
AGND AGND
AGNDAGND
AGNDAGND AGND
AGND
AGND
DB15_AUD_STK
DB15_AUD_STK
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
DB15_AUD_STK
+
Microphone Input
Stereo HP/Spkr out
AC’97 Audio
CD Analog Input
Line_In Analog Input