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Intel
®
820E Chipset
R
160 Design Guide
3.4.4. Clock Routing
Analog simulations are required to ensure that the clock net signal quality and skew are acceptable. The
system clock skew must be minimized. (The calculations and simulations for the example topology in
this document have a total clock skew of 200 ps and 150 ps of clock jitter). For a given design, the clock
distribution system, including the clock components, must be evaluated to ensure that these same values
are valid assumptions. Each processor’s datasheet specifies the clock signal quality requirements. To
help meet these specifications, comply with the following general guidelines:
• Tie the clock driver outputs if the clock buffer supports this mode of operation.
• Match the electrical length and type of traces on the PCB. (Microstrip and stripline may have
different propagation velocities.)
• Maintain consistent impedance for the clock traces.
Minimize the number of vias in each trace.
Minimize the number of different trace layers used to route the clocks.
Keep other traces away from clock traces.
• Lump the loads at the end of the trace if multiple components are to be supported by a single clock
output.
• Have equal loads at the end of each network.
The ideal way to route each clock trace is on the same single inner layer, next to a ground plane, isolated
from other traces, with the same total trace length, to the same type of single load, with an equal length
ground trace parallel to it, and driven by a zero-skew clock driver. When deviations from the ideal are
required, a good compromise is to go from a single layer to a pair of layers adjacent to power/ground
planes. The fewer number of layers on which the clocks are routed, the smaller the impedance difference
between each trace is likely to be. Maintaining an equal length and parallel ground trace for the
total
length of each
clock ensures a low-inductance ground return and produces the minimum current path
loop area. (The parallel ground trace will have lower inductance than the ground plane because of the
mutual inductance of the current in the clock trace.)
For the Intel 820E chipset/FC-PGA clock routing guidelines, refer to the
Intel
®
820 Chipset Design
Guide Addendum for the Intel
®
Pentium
®
III Processor for the PGA370 Socket. These guidelines can be
downloaded from the Intel website at http://developer.intel.com/design/chipsets/designex/298178.htm
.
3.5. Definitions of Flight Time Measurements/Corrections
and Signal Quality
Acceptable signal quality must be maintained over all operating conditions to ensure reliable operation.
Signal quality is defined by four parameters: overshoot, undershoot, settling limit, and ringback. Timings
are measured at the pins of the driver and receiver, while signal integrity is observed at the receiver chip
pad. When signal integrity at the pad violates the following guidelines and adjustments must be made to
flight time, the adjusted flight time obtained at the chip pad can be assumed to have been observed at the
package pin, usually with a small timing error penalty.