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GAME PORT
32
4.7K
R35
4.7K
R39
47
R38
1K
R33
1K
R32
R36
1K
R37
1K
12
MIDI_IN
12
J1BUTTON2
12
J2BUTTON2 5%
R24
2.2K
5%2.2K
R23
47
R34
5%2.2K
R22
5%2.2K
R21
12 JOY2Y
12
JOY1Y
12 MIDI_OUT
12
JOY2X
12
JOY1X
12
J1BUTTON1
12
J2BUTTON1
JOY1X_R
JOY2X_R
MIDI_OUT_R
JOY2Y_R
JOY1Y_R
MIDI_IN_R
J5
2
10
3
11
4
12
5
13
6
14
7
15
8
1
9
31
32
0.01UF
C69
25V
10%
10%
25V
C68
0.01UF
0.01UF
C67
25V
10%
0.01UF
C66
25V
10%
50V
C51
47PF
12
50V
C52
47PF
21
50V
47PF
C54
12
50V
C55
47PF
21
470PF
C53
C56
470PF
DRAWN BY:
LAST REVISED: SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
A
B
C
D
12345678
D
C
B
A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE Camino2
VCC5VCC5 VCC5 VCC5 VCC5 VCC5
VCC5
DB15_AUD_STK
+
+
+
+
Tie game port capacitors together and to SIO AVSS. Tie to system ground at only a single point.
Game Port