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Intel
®
820E Chipset
R
Design Guide 3
Contents
1.
Introduction ................................................................................................................................ 13
1.1. About This Design Guide .............................................................................................. 13
1.2. Reference Documents................................................................................................... 14
1.3. System Overview........................................................................................................... 15
1.3.1. Chipset Components................................................................................... 16
1.3.2. Bandwidth Summary ................................................................................... 17
1.3.3. System Configuration .................................................................................. 18
1.4. Platform Initiatives ......................................................................................................... 20
1.4.1. Direct Rambus RAM (RDRAM*) ................................................................. 20
1.4.2. Streaming SIMD Extensions ....................................................................... 20
1.4.3. AGP 2.0....................................................................................................... 20
1.4.4. Hub Interface............................................................................................... 20
1.4.5. Integrated LAN Controller............................................................................ 21
1.4.6. Ultra ATA/100 Support ................................................................................ 21
1.4.7. Expanded USB Support .............................................................................. 21
1.4.8. Manageability .............................................................................................. 21
1.4.9. AC’97 ........................................................................................................ 23
1.4.10. Low-Pin-Count (LPC) Interface ................................................................... 25
2. Layout/Routing Guidelines ......................................................................................................... 27
2.1. General Recommendations........................................................................................... 27
2.2. Component Quadrant Layout ........................................................................................ 27
2.3. Intel
®
820E Chipset Component Placement.................................................................. 29
2.4. Core Chipset Routing Recommendations..................................................................... 30
2.5. Source-Synchronous Strobing....................................................................................... 32
2.6. Differential Clocking/Strobing ........................................................................................ 33
2.7. Direct RDRAM* Interface .............................................................................................. 33
2.7.1. Stack-Up...................................................................................................... 34
2.7.2. Direct RDRAM* Layout Guidelines.............................................................. 34
2.7.2.1. RSL Routing ................................................................................... 35
2.7.2.2. RSL Termination............................................................................. 38
2.7.2.3. Direct RDRAM* Ground Plane Reference...................................... 39
2.7.2.4. Direct RDRAM* Connector Compensation..................................... 41
2.7.2.4.1. Direct RDRAM* Channel Connector Compensation
Enhancement Recommendation .................................. 47
2.7.2.5. RSL Signal Layer Alternation.......................................................... 49
2.7.2.6. Length Matching Methods .............................................................. 50
2.7.2.7. Via Compensation .......................................................................... 52
2.7.2.8. Length Matching and Via Compensation Example......................... 52
2.7.3. Direct RDRAM* Reference Voltage............................................................. 54
2.7.4. High-Speed CMOS Routing ........................................................................ 54
2.7.4.1. SIO Routing .................................................................................... 55
2.7.4.2. Suspend-to-RAM Shunt Transistor................................................. 56
2.7.5. Direct RDRAM* Clock Routing .................................................................... 57
2.7.6. Direct RDRAM* Design Checklist ............................................................... 57
2.8. AGP 2.0 .........................................................................................................................60
2.8.1. AGP Interface Signal Groups ...................................................................... 60
2.8.2. 1× Timing Domain Routing Guidelines........................................................ 62