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Intel
®
820E Chipset
R
184 Design Guide
6.1.2. Power Delivery of Intel
®
820E Chipset Customer Reference
Board
Figure 101 shows the power delivery architecture for the Intel 820E Chipset Reference Board. This
power delivery architecture supports the Instantly Available PC Design Guidelines via the Suspend-to-
RAM (STR) state. During STR, only the necessary devices are powered. These devices include main
memory, the ICH2 resume well, PCI wake devices (via 3.3 V
AUX
), and USB. (USB can be powered only
if sufficient standby power is available.) To ensure that enough power is available during STR, a
thorough power budget must be completed. The power requirements must include each device’s power
requirements, both in the suspend and full-power states. The power requirements must be compared with
the power budget available from the power supply. Due to the requirements of main memory and PCI
3.3 V
AUX
—and possibly other devices in the system—it is necessary to create a dual power rail.
Figure 101. Intel
®
820E Chipset Power Delivery Example
2.5V
1.8V
FWH Flash BIOS
Core: 3.3V
67mA S0, S1
MCH Core: 1.8V
MCH Hub I/F I/O: 1.8V
950mA S0, S1
MCH VDDQ: 1.5V/3.3V*
2A S0, S1
VccCPU-VRM out
10mA S0, S1
Vcc1_8-Hub I/F I/O: 1.8V
300mA S0, S1
V5Ref: 5V
<10uA S0, S1
RDRAM Core: 2.5V
2.0A S0, S1; 32ma S3
VccSus3_3-ICH Resume:
3.3V
20mA S0, S1; 300uA S3,S5
VccRTC-ICH RTC: Vbat
<4uA S0, S1, S3, S5
VCC CMOS: 1.8V
3mA S0, S1, S3
RDRAM VTerm: 1.8V
704mA S0, S1
LPC Super I/O: 3.3V
CK133-3.3:
3.3V
CK133-2.5:
2.5V
PCI 3.3Vaux: 3.3V
1.5A S0, S1; 435ma S3, S5
AC'97 Audio
Codec: 5V
USB Cable
Power: 5V
PGA370 Core: VCC_VID
22A** S0, S1
PGA370 VTT: 1.5V
2.7A** S0, S1
DRCG: 3.3V
100mA S0, S1
ATX P/S
with 1A 5VSB
5VSB
5V
3.3V 12V
VTT
Regulator
VRM
2.5VSBY
Regulator
1.8V
Regulator
VDDQ
Regulator
3.3VSB
Regulator
* Vddq also connects to the AGP connector. 2A is the TOTAL VDDQ current requirement.
** Refer to the Pentium
®
III processor datasheet for power requirement considerations for PGA370 designs.
The Pentium
®
III processor datasheet can be found at: http://developer.intel.com/design/PentiumIII/datashts/
Shaded regulators/components are on in S3, S5 (Note RDRAM core and VCC CMOS must be OFF in S5)
VCC2_5 Voltage
Regulator: 2.5V
5V Dual
Switch
VccSus1_8-ICH Resume:
1.8V
210mA S0, S120mA S3, S5
Vcc3_3: 3.3V
<300mA S0, S1
ICH2
V5RefSus: 5VSB
<10uA S0,S1,S3,S5
1.8VSB
Regulator
Diode for
Sequencing
MBR 2.0 82562EH,
82562ET, (PHY) +
Modem Codec S0, S1,
S3, S5
12V, 3.3V,
3.3VSB, 5V,
5VDUAL
CPU CMOS P/Us: 1.5V
Pwr_Delivery
LEGEND:
ATX Power Planes Intel
®
820E Chipset Power Planes
5VSB 5V Dual
5V VCCVID
3.3V VTT
12V 2.5VSBY
1.8V
VDDQ
3.3VSB
2.5V
1.8VSB