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104 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
00001813h R/W Region Configuration Range 3 MSR
(RCONF3_MSR)
00000000_00000000h Page 169
Warm Start Value:
xxxxx000_xxxxx0xxh
00001814h R/W Region Configuration Range 4 MSR
(RCONF4_MSR)
00000000_00000000h Page 169
Warm Start Value:
xxxxx000_xxxxx0xxh
00001815h R/W Region Configuration Range 5 MSR
(RCONF5_MSR)
00000000_00000000h Page 169
Warm Start Value:
xxxxx000_xxxxx0xxh
00001816h R/W Region Configuration Range 6 MSR
(RCONF6_MSR)
00000000_00000000h Page 169
Warm Start Value:
xxxxx000_xxxxx0xxh
00001817h R/W Region Configuration Range 7 MSR
(RCONF7_MSR)
00000000_00000000h Page 169
Warm Start Value:
xxxxx000_xxxxx0xxh
00001881h R/W x86 Control Register 1 MSR (CR1_MSR) 00000000_xxxxxxxxh Page 172
00001882h R/W x86 Control Register 2 MSR (CR2_MSR) 00000000_xxxxxxxxh Page 172
00001883h R/W x86 Control Register 3 MSR (CR3_MSR) 00000000_xxxxxxxxh Page 172
00001884h R/W x86 Control Register 4 MSR (CR4_MSR) 00000000_xxxxxxxxh Page 172
00001890h R/W Data Cache Index MSR (DC_INDEX_MSR) 00000000_00000000h Page 172
00001891h R/W Data Cache Data MSR (DC_DATA_MSR) 00000000_00000000h Page 173
00001892h R/W Data Cache Tag MSR (DC_TAG_MSR) 00000000_00000000h Page 173
00001893h R/W Data Cache Tag with Increment MSR
(DC_TAG_I_MSR)
00000000_00000000h Page 174
00001894h WO Data/Instruction Cache Snoop Register
(SNOOP_MSR)
00000000_xxxxxxxxh Page 175
00001898h R/W L1 Data TLB Index Register
(L1DTLB_INDEX_MSR)
00000000_00000000h Page 175
00001899h R/W L1 Data TLB Least Recently Used MSR
(L1DTLB_LRU_MSR)
00000000_00000000h Page 176
0000189Ah R/W L1 Data TLB Entry MSR (L1DTLB_ENTRY_MSR) 00000000_00000000h Page 177
0000189Bh R/W L1 Data TLB Entry with Increment MSR
(L1DTLB_ENTRY_I_MSR)
00000000_00000000h Page 178
0000189Ch R/W L2 TLB/DTE/PTE Index MSR
(L2TLB_INDEX_MSR)
00000000_00000000h Page 178
0000189Dh R/W L2 TLB/DTE/PTE Least Recently Used MSR
(L2TLB_LRU_MSR)
00000000_00000000h Page 179
0000189Eh R/W L2 TLB/DTE/PTE Entry MSR
(L2TLB_ENTRY_MSR)
00000000_00000000h Page 180
0000189Fh R/W L2 TLB/DTE/PTE Entry with Increment MSR
(L2TLB_ENTRY_I_MSR)
00000000_00000000h Page 182
000018C0h R/W Data Memory Subsystem Built-In Self-Test MSR
(DM_BIST_MSR)
00000000_00000000h Page 182
00001900h R/W Bus Controller Configuration 0 MSR
(BC_CONFIG0_MSR)
00000000_00000111h Page 183
Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address Type Register Name Reset Value Reference