Filter
Top Products
184 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.90 Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR)
This register is reserved. Write as read.
19:14 RSVD Reserved. Write as read.
13 CLK_ONS CPU Core Clocks On during Suspend.
0: All CPU Core clocks off during Suspend. (Default)
1: All CPU Core clocks on during Suspend.
12 SUSP Suspend Active. Enable Suspend input.
0: Ignore Suspend input. (Default)
1: Enable Suspend input.
11:9 RSVD Reserved. Write as read.
8 RTSC_SUSP Real Time Stamp Counter Counts during Suspend.
0: Disable.
1: Enable. (Default)
7 RSVD Reserved. Write as read.
6TSC_DMM Time Stamp Counter Counts during DMM.
0: Disable. (Default)
1: Enable.
5TSC_SUSP Time Stamp Counter Counts during Suspend.
0: Disable. (Default)
1: Enable.
4TSC_SMM Time Stamp Counter Counts during SMM.
0: Disable.
1: Enable. (Default)
3:2 RSVD Reserved. Write as read.
1ISNINV Ignore Snoop Invalidate. Allow the CPU Core to ignore the INVALIDATE bit in the GLIU
snoop packet. When a snoop hits to a dirty cache line it is evicted, regardless of the state
of the INVALIDATE bit in the GLIU packet.
0: Process snoop packet.
1: Ignore snoop packet. (Default)
0SNOOP Instruction Memory (IM) to Data Memory (DM) Snooping. Allow code fetch snoops
from the IM to the DM cache.
0: Disable.
1: Enable. (Default)
MSR Address 00001901h
Typ e R /W
Reset Value 00000000_00000000h
BC_CONFIG0_MSR Bit Descriptions (Continued)
Bit Name Description