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198 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR)
This register contains the status of the bus controller breakpoints. When a breakpoint occurs, the corresponding status bit
is set in this register. The status bits remain set until cleared by an MSR write.
5.5.2.109 Bus Controller Debug Register 7 MSR (BDR7_MSR)
This register is the bus controller breakpoint control/enable register.
MSR Address 00001976h
Typ e R /W
Reset Value 00000000_00000000h
BDR6_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD T3 T2 T1 T0
BDR6_MSR Bit Descriptions
Bit Name Description
63:4 RSVD Reserved. (Default = 0)
3T3 Breakpoint 3 Triggered. A 1 Indicates that breakpoint 3 has triggered. Write to clear.
(Default = 0)
2T2 Breakpoint 2 Triggered. A 1 Indicates that breakpoint 2 has triggered. Write to clear.
(Default = 0)
1T1 Breakpoint 1 Triggered. A 1 Indicates that breakpoint 1 has triggered. Write to clear.
(Default = 0)
0T0 Breakpoint 0 Triggered. A 1 Indicates that breakpoint 0 has triggered. Write to clear.
(Default = 0)
MSR Address 00001977h
Typ e R /W
Reset Value 00000000_00000000h
BDR7_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
TYPE3 TYPE2 TYPE1 TYPE0 RSVD E3 E2 E1 E0
BDR7_MSR Bit Descriptions
Bit Name Description
63:32 RSVD Reserved. (Default = 0)