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AMD Geode™ LX Processors Data Book 193
CPU Core Register Descriptions
33234H
5.5.2.103 Power Mode MSR (PMODE_MSR)
This MSR enables some modules to turn their clocks off when they are idle to save power. Most of these bits are off by
default. It is recommended that they be set by BIOS.
MSR Address 00001930h
Typ e R /W
Reset Value 00000000_00000300h
PMODE_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
IRS_IF
IRS_IMTAG
IRS_IMDATA
RSVD
FPU_EX
FPU_FP
RSVD
BCL2_MSR
BCL2_GATED
PMODE_MSR Bit Descriptions
Bit Name Description
63:19 RSVD Reserved.
18 IRS_IF Reserved, Instruction Fetch. Reserved for possible future clock gating of IF.
(Default = 0)
17 IRS_IMTAG Reserved, Instruction Memory Subsystem. Reserved for possible future clock gating
IM tag. (Default = 0)
16 IRS_IMDATA Instruction Memory Subsystem Data. When bit is set, IM may turn off the clock when
IM_DATA is idle. (Default = 0)
9FPU_EX FPU EX. When bit is set, FPU may turn off the clock to FPU Region 1 when FP_EX is
idle. (Default = 1)
8FPU_FP FPU_FP. When bit is set, FPU may turn off the clock to FPU Region 2 when FPU is idle.
(Default = 1)
1 BCL2_MSR BCL2 MSR. When bit is set, BCL2 may turn off the clock to BC Region 1 when
BCL2_MSR is idle. (Default = 0)
0 BCL2_GATED BCL2 Gated. When bit is set, BCL2 may turn off the clock to BC Region 2 when BCL2 is
idle. (Default = 0)