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56 AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.1.3 GLD SMI MSR (GLD_MSR_SMI)
The flags are set with internal conditions. The internal conditions are always capable of setting the flag, but if the mask is 1,
the flagged condition will not trigger the SMI signal. Reads to the flags return the value. Write = 1 to the flag, clears the
value. Write = 0 has no effect on the flag.
MSR Address GLIU0: 10002002h
GLIU1: 40002002h
Typ e R /W
Reset Value 00000000_00000001h
GLD
_MSR_SMI Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
SFLAG4
SFLAG3
SFLAG2
SFLAG1
SFLAG0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
SMASK4
SMASK3
SMASK2
SMASK1
SMASK0
GLD_MSR_SMI Bit Descriptions
Bit Name Description
63:37 RSVD Reserved.
36 SFLAG4 SMI Flag4. If high, records that an SMI was generated due to a Statistic Counter 3
(GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh) event. Write 1 to clear; writing 0 has
no effect. SMASK4 (bit 4) must be low to generate SMI and set flag.
35 SFLAG3 SMI Flag3. If high, records that an SMI was generated due to a Statistic Counter 2
(GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h) event. Write 1 to clear; writing 0 has
no effect. SMASK3 (bit 3) must be low to generate SMI and set flag.
34 SFLAG2 SMI Flag2. If high, records that an SMI was generated due to a Statistic Counter 1
(GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h) event. Write 1 to clear; writing 0 has
no effect. SMASK2 (bit 2) must be low to generate SMI and set flag.
33 SFLAG1 SMI Flag1. If high, records that an SMI was generated due to a Statistic Counter 0
(GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event. Write 1 to clear; writing 0 has
no effect. SMASK1 (bit 1) must be low to generate SMI and set flag.
32 SFLAG0 SMI Flag0. Unexpected Type (HW Emulation).
31:5 RSVD Reserved.
4 SMASK4 SMI Mask4. Write 0 to enable SFLAG4 (bit 37) and to allow a Statistic Counter 3 (GLIU0
MSR 100000ACh, GLIU1 MSR 400000ACh) event to generate an SMI.
3 SMASK3 SMI Mask3. Write 0 to enable SFLAG3 (bit 36) and to allow a Statistic Counter 2 (GLIU0
MSR 100000A8h, GLIU1 MSR 400000A8h) event to generate an SMI.
2 SMASK2 SMI Mask2. Write 0 to enable SFLAG2 (bit 34) and to allow a Statistic Counter 1 (GLIU0
MSR 100000A4h, GLIU1 MSR 400000A4h) event to generate an SMI.
1 SMASK1 SMI Mask1. Write 0 to enable SFLAG1 (bit 33) and to allow a Statistic Counter 0 (GLIU0
MSR 100000A0h, GLIU1 MSR 400000A0h) event to generate an SMI.
0 SMASK0 SMI Mask0. Unexpected Type (HW Emulation).