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AMD Geode™ LX Processors Data Book 381
Display Controller Register Descriptions
33234H
6.6.21.5 Color Plane Enable
6.6.21.6 Horizontal Pel Panning
Index 12h
Typ e R /W
Reset Value xxh
Color Plane Enable Register Bit Descriptions
Bit Name Description
7:4 RSVD Reserved.
3 EN_CO_PN3 Enable Color Plane 3. This bit enables color plane 3. It is ANDed with it corresponding
pixel bit and the resulting 4-bit value is used as the address into the EGA palette.
2 EN_CO_PN2 Enable Color Plane 2. This bit enables color plane 2. It is ANDed with it corresponding
pixel bit and the resulting 4-bit value is used as the address into the EGA palette.
1 EN_CO_PN1 Enable Color Plane 1. This bit enables color plane 1. It is ANDed with it corresponding
pixel bit and the resulting 4-bit value is used as the address into the EGA palette.
0 EN_CO_PN0 Enable Color Plane 0. This bit enables color plane 0. It is ANDed with it corresponding
pixel bit and the resulting 4-bit value is used as the address into the EGA palette.
Index 13h
Typ e R /W
Reset Value xxh
Horizontal Pel Panning Register Bit Descriptions
Bit Name Description
7:4 RSVD Reserved.
3:0 HPP Horizontal Pel Panning: This field specifies how many pixels the screen image should
be shifted to the left by.
Bits [3:0] Mode 13h
Panning
9-Wide Text Mode
Panning
Panning for All
Other Modes
0000 0 1 0
0001 -- 2 1
0010 1 3 2
0011 -- 4 3
0100 2 5 4
0101 -- 6 5
0110 3 7 6
0111 -- 8 7
1000 -- 0 -
1001 -- -- --
1010 -- -- --
1011 -- -- --
1100 -- -- --
1101 -- -- --
1110 -- -- --
1111 -- -- --